An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Lingfeng Li, Satoshi Goto, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages623-626
Number of pages4
Volume1
Publication statusPublished - 2005
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai
Duration: 2005 Jan 182005 Jan 21

Other

Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CityShanghai
Period05/1/1805/1/21

Fingerprint

Data storage equipment
Static random access storage
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Li, L., Goto, S., & Ikenaga, T. (2005). An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 1, pp. 623-626). [1466238]

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. / Li, Lingfeng; Goto, Satoshi; Ikenaga, Takeshi.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1 2005. p. 623-626 1466238.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, L, Goto, S & Ikenaga, T 2005, An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. vol. 1, 1466238, pp. 623-626, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, 05/1/18.
Li L, Goto S, Ikenaga T. An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1. 2005. p. 623-626. 1466238
Li, Lingfeng ; Goto, Satoshi ; Ikenaga, Takeshi. / An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1 2005. pp. 623-626
@inproceedings{c5a24493672949d7ad60f8f1da46e1fa,
title = "An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC",
abstract = "In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.",
author = "Lingfeng Li and Satoshi Goto and Takeshi Ikenaga",
year = "2005",
language = "English",
isbn = "0780387368",
volume = "1",
pages = "623--626",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

}

TY - GEN

T1 - An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

AU - Li, Lingfeng

AU - Goto, Satoshi

AU - Ikenaga, Takeshi

PY - 2005

Y1 - 2005

N2 - In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.

AB - In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.

UR - http://www.scopus.com/inward/record.url?scp=84861419180&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84861419180&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84861419180

SN - 0780387368

SN - 9780780387362

VL - 1

SP - 623

EP - 626

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ER -