An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Lingfeng Li, Satoshi Goto, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.

Original languageEnglish
Title of host publicationProceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages623-626
Number of pages4
Publication statusPublished - 2005 Dec 1
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: 2005 Jan 182005 Jan 21

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume1

Conference

Conference2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CountryChina
CityShanghai
Period05/1/1805/1/21

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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