An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Lingfeng Li; Satoshi Goto; Takeshi Ikenaga

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Lingfeng Li^*, Satoshi Goto, Takeshi Ikenaga

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Citations (Scopus)

Abstract

In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.

Original language	English
Title of host publication	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages	623-626
Number of pages	4
Publication status	Published - 2005 Dec 1
Event	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China Duration: 2005 Jan 18 → 2005 Jan 21

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	1

Conference

Conference	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Country/Territory	China
City	Shanghai
Period	05/1/18 → 05/1/21

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Cite this

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. / Li, Lingfeng; Goto, Satoshi; Ikenaga, Takeshi.

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. 2005. p. 623-626 1466238 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, L, Goto, S & Ikenaga, T 2005, An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466238, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1, pp. 623-626, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 05/1/18.

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An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Abstract

Publication series

Conference

ASJC Scopus subject areas

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