An efficient decoder architecture for cyclic non-binary LDPC codes

Yichao Lu; Guifen Tian; Satoshi Goto

doi:10.1109/ISCAS.2014.6865149

An efficient decoder architecture for cyclic non-binary LDPC codes

Yichao Lu, Guifen Tian, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper proposes a hybrid message-passing decoding algorithm which consumes very low computational complexity, while achieving competitive error performance compared with conventional min-max algorithm. Simulation result on a (255,175) cyclic code shows that this algorithm obtains at least 0.5dB coding gain over other state-of-the-art low-complexity non-binary LDPC (NB-LDPC) decoding algorithms. Based on this algorithm, a partial-parallel decoder architecture is implemented for cyclic NB-LDPC codes, where the variable node units are redesigned and the routing network is optimized for the proposed algorithm. Synthesis results demonstrate that about 24.3% gates and 12% memories can be saved over previous works.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	397-400
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865149
Publication status	Published - 2014
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC Duration: 2014 Jun 1 → 2014 Jun 5

Other

Other	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
City	Melbourne, VIC
Period	14/6/1 → 14/6/5

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISCAS.2014.6865149

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Lu, Y, Tian, G & Goto, S 2014, An efficient decoder architecture for cyclic non-binary LDPC codes. in Proceedings - IEEE International Symposium on Circuits and Systems., 6865149, Institute of Electrical and Electronics Engineers Inc., pp. 397-400, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, 14/6/1. https://doi.org/10.1109/ISCAS.2014.6865149

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abstract = "This paper proposes a hybrid message-passing decoding algorithm which consumes very low computational complexity, while achieving competitive error performance compared with conventional min-max algorithm. Simulation result on a (255,175) cyclic code shows that this algorithm obtains at least 0.5dB coding gain over other state-of-the-art low-complexity non-binary LDPC (NB-LDPC) decoding algorithms. Based on this algorithm, a partial-parallel decoder architecture is implemented for cyclic NB-LDPC codes, where the variable node units are redesigned and the routing network is optimized for the proposed algorithm. Synthesis results demonstrate that about 24.3% gates and 12% memories can be saved over previous works.",

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year = "2014",

doi = "10.1109/ISCAS.2014.6865149",

language = "English",

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AB - This paper proposes a hybrid message-passing decoding algorithm which consumes very low computational complexity, while achieving competitive error performance compared with conventional min-max algorithm. Simulation result on a (255,175) cyclic code shows that this algorithm obtains at least 0.5dB coding gain over other state-of-the-art low-complexity non-binary LDPC (NB-LDPC) decoding algorithms. Based on this algorithm, a partial-parallel decoder architecture is implemented for cyclic NB-LDPC codes, where the variable node units are redesigned and the routing network is optimized for the proposed algorithm. Synthesis results demonstrate that about 24.3% gates and 12% memories can be saved over previous works.

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BT - Proceedings - IEEE International Symposium on Circuits and Systems

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An efficient decoder architecture for cyclic non-binary LDPC codes

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