An efficient decoder architecture for cyclic non-binary LDPC codes

Yichao Lu, Guifen Tian, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a hybrid message-passing decoding algorithm which consumes very low computational complexity, while achieving competitive error performance compared with conventional min-max algorithm. Simulation result on a (255,175) cyclic code shows that this algorithm obtains at least 0.5dB coding gain over other state-of-the-art low-complexity non-binary LDPC (NB-LDPC) decoding algorithms. Based on this algorithm, a partial-parallel decoder architecture is implemented for cyclic NB-LDPC codes, where the variable node units are redesigned and the routing network is optimized for the proposed algorithm. Synthesis results demonstrate that about 24.3% gates and 12% memories can be saved over previous works.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages397-400
Number of pages4
ISBN (Print)9781479934324
DOIs
Publication statusPublished - 2014
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC
Duration: 2014 Jun 12014 Jun 5

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CityMelbourne, VIC
Period14/6/114/6/5

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Lu, Y., Tian, G., & Goto, S. (2014). An efficient decoder architecture for cyclic non-binary LDPC codes. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 397-400). [6865149] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865149