An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power

Xin Jiang, Ran Zhang, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The application of 3D Networks-on-chip (NoCs) has been proved to be an effective solution to the global communication of 3D IC integration, while the design of NoC topologies has played a critical role to increase interconnection performance. In this work, we propose a new procedure for designing application specific irregular 3D NoC topologies which achieve significant performance improvement. The objective is to improve both communication latency and power consumption under several 3D constraints. We propose a two-stage design model based on a series of efficient algorithms to explore the optimized topology in a large scale searching space. Numerical experimental results show that the topologies by our design algorithm achieve more performance improvement (about 31.5%) than the classical topologies and the proposed algorithm also proves to be a time efficient method for exploration in the large solution space.

Original languageEnglish
Title of host publicationProceedings of International Conference on ASIC
Pages535-538
Number of pages4
DOIs
Publication statusPublished - 2011
Event2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen
Duration: 2011 Oct 252011 Oct 28

Other

Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
CityXiamen
Period11/10/2511/10/28

Fingerprint

Topology
Communication
Electric power utilization
Network-on-chip

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power. / Jiang, Xin; Zhang, Ran; Watanabe, Takahiro.

Proceedings of International Conference on ASIC. 2011. p. 535-538 6157240.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jiang, X, Zhang, R & Watanabe, T 2011, An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power. in Proceedings of International Conference on ASIC., 6157240, pp. 535-538, 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, 11/10/25. https://doi.org/10.1109/ASICON.2011.6157240
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