An efficient hardware accelerator for power grid simulation

Taiki Hashizume*, Hisako Sugano, Shinichi Nishizawa, Masaya Yoshikawa, Masahiro Fukui

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

With the deep submicron technologies, IR drop and electromigration have become remarkable by decreasing of the power supply voltage. Therefore, power grid optimization becomes important to achieve the stable operation of Large Scale Integration (LSI). However, it requires large computation time. In this paper, we propose a novel power grid simulation technique which can be applied to a large scale power grid. The proposal technique achieves "High speed processing by hardware accelerator" and "Realization of high accuracy computation with fixed point arithmetic". The proposed power grid simulation algorithm achieves 32 times more high speed processing than software processing. The accuracy is proven by experimental comparison with SPICE simulation.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages2994-2997
Number of pages4
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan, Province of China
Duration: 2009 May 242009 May 27

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/TerritoryTaiwan, Province of China
CityTaipei
Period09/5/2409/5/27

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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