An efficient hardware accelerator for power grid simulation

Taiki Hashizume; Hisako Sugano; Shinichi Nishizawa; Masaya Yoshikawa; Masahiro Fukui

doi:10.1109/ISCAS.2009.5118432

An efficient hardware accelerator for power grid simulation

Taiki Hashizume^*, Hisako Sugano, Shinichi Nishizawa, Masaya Yoshikawa, Masahiro Fukui

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

With the deep submicron technologies, IR drop and electromigration have become remarkable by decreasing of the power supply voltage. Therefore, power grid optimization becomes important to achieve the stable operation of Large Scale Integration (LSI). However, it requires large computation time. In this paper, we propose a novel power grid simulation technique which can be applied to a large scale power grid. The proposal technique achieves "High speed processing by hardware accelerator" and "Realization of high accuracy computation with fixed point arithmetic". The proposed power grid simulation algorithm achieves 32 times more high speed processing than software processing. The accuracy is proven by experimental comparison with SPICE simulation.

Original language	English
Title of host publication	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages	2994-2997
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2009.5118432
Publication status	Published - 2009
Externally published	Yes
Event	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan, Province of China Duration: 2009 May 24 → 2009 May 27

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/Territory	Taiwan, Province of China
City	Taipei
Period	09/5/24 → 09/5/27

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISCAS.2009.5118432

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An efficient hardware accelerator for power grid simulation. / Hashizume, Taiki; Sugano, Hisako; Nishizawa, Shinichi et al.

2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. 2009. p. 2994-2997 5118432 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hashizume, T, Sugano, H, Nishizawa, S, Yoshikawa, M & Fukui, M 2009, An efficient hardware accelerator for power grid simulation. in 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5118432, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 2994-2997, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, Province of China, 09/5/24. https://doi.org/10.1109/ISCAS.2009.5118432

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title = "An efficient hardware accelerator for power grid simulation",

abstract = "With the deep submicron technologies, IR drop and electromigration have become remarkable by decreasing of the power supply voltage. Therefore, power grid optimization becomes important to achieve the stable operation of Large Scale Integration (LSI). However, it requires large computation time. In this paper, we propose a novel power grid simulation technique which can be applied to a large scale power grid. The proposal technique achieves {"}High speed processing by hardware accelerator{"} and {"}Realization of high accuracy computation with fixed point arithmetic{"}. The proposed power grid simulation algorithm achieves 32 times more high speed processing than software processing. The accuracy is proven by experimental comparison with SPICE simulation.",

author = "Taiki Hashizume and Hisako Sugano and Shinichi Nishizawa and Masaya Yoshikawa and Masahiro Fukui",

year = "2009",

doi = "10.1109/ISCAS.2009.5118432",

language = "English",

isbn = "9781424438280",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "2994--2997",

booktitle = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009",

note = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 ; Conference date: 24-05-2009 Through 27-05-2009",

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TY - GEN

T1 - An efficient hardware accelerator for power grid simulation

AU - Hashizume, Taiki

AU - Sugano, Hisako

AU - Nishizawa, Shinichi

AU - Yoshikawa, Masaya

AU - Fukui, Masahiro

PY - 2009

Y1 - 2009

N2 - With the deep submicron technologies, IR drop and electromigration have become remarkable by decreasing of the power supply voltage. Therefore, power grid optimization becomes important to achieve the stable operation of Large Scale Integration (LSI). However, it requires large computation time. In this paper, we propose a novel power grid simulation technique which can be applied to a large scale power grid. The proposal technique achieves "High speed processing by hardware accelerator" and "Realization of high accuracy computation with fixed point arithmetic". The proposed power grid simulation algorithm achieves 32 times more high speed processing than software processing. The accuracy is proven by experimental comparison with SPICE simulation.

AB - With the deep submicron technologies, IR drop and electromigration have become remarkable by decreasing of the power supply voltage. Therefore, power grid optimization becomes important to achieve the stable operation of Large Scale Integration (LSI). However, it requires large computation time. In this paper, we propose a novel power grid simulation technique which can be applied to a large scale power grid. The proposal technique achieves "High speed processing by hardware accelerator" and "Realization of high accuracy computation with fixed point arithmetic". The proposed power grid simulation algorithm achieves 32 times more high speed processing than software processing. The accuracy is proven by experimental comparison with SPICE simulation.

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U2 - 10.1109/ISCAS.2009.5118432

DO - 10.1109/ISCAS.2009.5118432

M3 - Conference contribution

AN - SCOPUS:70350167202

SN - 9781424438280

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 2994

EP - 2997

BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

T2 - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

Y2 - 24 May 2009 through 27 May 2009

ER -

An efficient hardware accelerator for power grid simulation

Abstract

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