An efficient hardware architecture for full-search variable block size motion estimation in H.264/AVC

Seung Man Pyen, Kyeong Yuk Min, Jong Wha Chong, Satoshi Goto

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In this paper, we propose a high speed hardware architecture for the implementation of full-search variable block size motion estimation (VBSME) suitable for high quality video compression. In the high-quality video with large frame size and search range, the memory bandwidth is mainly responsible for throughput limitations and power consumption in VBSME. The proposed architecture is designed for reducing the memory bandwidth by adopting "meander"-like scan for a high overlapped data of the search area and using on-chip memory to reuse the overlapped data. We can reuse the previous candidate block of 94% to the current one and save about 23% memory access cycles in a search range of [-16, +15]. The architecture has been prototyped in Verilog HDL, simulated by ModelSim and synthesized by Synopsys Design Compiler with Samsung 0.18 Sum standard cell library. Under a clock frequency of 51 MHz, The simulation result shows that the architecture can achieve the real-time processing of 720x576 picture size at 30fps with the search range of [-16-+15].

Original languageEnglish
Pages (from-to)554-563
Number of pages10
JournalUnknown Journal
Volume4292 LNCS - II
Publication statusPublished - 2006

ASJC Scopus subject areas

  • Computer Science(all)
  • Biochemistry, Genetics and Molecular Biology(all)
  • Theoretical Computer Science

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    Pyen, S. M., Min, K. Y., Chong, J. W., & Goto, S. (2006). An efficient hardware architecture for full-search variable block size motion estimation in H.264/AVC. Unknown Journal, 4292 LNCS - II, 554-563.