An efficient highly adaptive and deadlock-free routing algorithm for 3D network-on-chip

Lian Zengy, Tieyuan Pan, Xin Jiang, Takahiro Watanabe

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

As the semiconductor technology continues to develop, hundreds of cores will be deployed on a single die in the future Chip-Multiprocessors (CMPs) design. Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide impressive high performance. An efficient and deadlock-free routing algorithm is a critical to achieve the high performance of network-on-chip. Traditional methods based on deterministic and turn model are deadlock-free, but they are unable to distribute the traffic loads over the network. In this paper, we propose an efficient, adaptive and deadlock-free algorithm (EAR) based on a novel routing selection strategy in 3D NoC, which can distribute the traffic loads not only in intra-layers but also in inter-layers according to congestion information and path diversity. Simulation results show that the proposed method achieves the significant performance improvement compared with others.

Original languageEnglish
Pages (from-to)1334-1344
Number of pages11
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE99A
Issue number7
DOIs
Publication statusPublished - 2016 Jul 1

Fingerprint

Deadlock
Routing algorithms
Routing Algorithm
High Performance
Traffic
Chip multiprocessors
Congestion
Semiconductors
Routing
Continue
Die
Semiconductor materials
Three-dimensional
Path
Network on chip
Network-on-chip
Simulation
Model

Keywords

  • 3D network-on-chip
  • Adaptive routing
  • Congestion-balance
  • Deadlock-free
  • Path diversity

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

An efficient highly adaptive and deadlock-free routing algorithm for 3D network-on-chip. / Zengy, Lian; Pan, Tieyuan; Jiang, Xin; Watanabe, Takahiro.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E99A, No. 7, 01.07.2016, p. 1334-1344.

Research output: Contribution to journalArticle

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