An energy efficiency 4-bit multiplier with two-phase non-overlap clock driven charge recovery logic

Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara

    Research output: Contribution to journalArticle

    7 Citations (Scopus)

    Abstract

    A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a high-speed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. PBL belongs to boost logic family, which includes boost logic, enhanced boost logic and subthreshold boost logic. In this paper, PBL has been compared with other charge-recovery logic technologies. To demonstrate the performance of PBL structure, a 4-bit pipeline multiplier is designed and fabricated with 0.18 μm CMOS process technology. The simulation results indicate that the 4-bit multiplier can work at a frequency of 1.8 GHz, while the measurement of test chip is at operation frequency of 161 MHz, and the power dissipation at 161 MHz is 772 μW.

    Original languageEnglish
    Pages (from-to)605-612
    Number of pages8
    JournalIEICE Transactions on Electronics
    VolumeE94-C
    Issue number4
    DOIs
    Publication statusPublished - 2011 Apr

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    Keywords

    • Adiabatic logic
    • Boost logic
    • Low energy dissipation
    • Pipeline multiplier

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

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