An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)

    Abstract

    In this paper, we first propose a huddle-based distributed-register architecture (HDR architecture), an island-based distributed-register architecture for multi-cycle interconnect communications where we can develop several energy-saving techniques. Next, we propose an energy-efficient high-level synthesis algorithm for HDR architectures focusing on multiple supply voltages. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which is composed of functional units, registers, controller, and level converters, are very naturally generated using floorplanning results. By assigning high supply voltage to critical huddles and low supply voltage to non-critical huddles, we can finally have energy-efficient floorplan-aware high-level synthesis. Experimental results show that our algorithm achieves 45% energy-saving compared with the conventional distributed-register architectures and conventional algorithms.

    Original languageEnglish
    Title of host publicationISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems
    Pages576-579
    Number of pages4
    DOIs
    Publication statusPublished - 2012
    Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul
    Duration: 2012 May 202012 May 23

    Other

    Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
    CitySeoul
    Period12/5/2012/5/23

    Fingerprint

    Energy conservation
    Electric potential
    Scheduling
    Controllers
    High level synthesis
    Communication

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Abe, S. Y., Yanagisawa, M., & Togawa, N. (2012). An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. In ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems (pp. 576-579). [6272096] https://doi.org/10.1109/ISCAS.2012.6272096

    An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. / Abe, Shin Ya; Yanagisawa, Masao; Togawa, Nozomu.

    ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. 2012. p. 576-579 6272096.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abe, SY, Yanagisawa, M & Togawa, N 2012, An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. in ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems., 6272096, pp. 576-579, 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, 12/5/20. https://doi.org/10.1109/ISCAS.2012.6272096
    Abe, Shin Ya ; Yanagisawa, Masao ; Togawa, Nozomu. / An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. 2012. pp. 576-579
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