An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures

Research output: Contribution to conferencePaperpeer-review

8 Citations (Scopus)

Abstract

In this paper, we first propose a huddle-based distributed-register architecture (HDR architecture), an island-based distributed-register architecture for multi-cycle interconnect communications where we can develop several energy-saving techniques. Next, we propose an energy-efficient high-level synthesis algorithm for HDR architectures focusing on multiple supply voltages. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which is composed of functional units, registers, controller, and level converters, are very naturally generated using floorplanning results. By assigning high supply voltage to critical huddles and low supply voltage to non-critical huddles, we can finally have energy-efficient floorplan-aware high-level synthesis. Experimental results show that our algorithm achieves 45% energy-saving compared with the conventional distributed-register architectures and conventional algorithms.

Original languageEnglish
Pages576-579
Number of pages4
DOIs
Publication statusPublished - 2012 Sep 28
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 2012 May 202012 May 23

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period12/5/2012/5/23

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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