An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Shin Ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture) that integrates dynamic multiple supply voltages and interconnection delays into high-level synthesis. Next, we propose a high-level synthesis algorithm for AVHDR architectures. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which abstracts modules placed close to each other, are naturally generated using floorplanning. Low-supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Experimental results show that our algorithm achieves 50% energy-saving compared with conventional algorithms.

    Original languageEnglish
    Title of host publication2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
    DOIs
    Publication statusPublished - 2013
    Event2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu
    Duration: 2013 Apr 222013 Apr 24

    Other

    Other2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
    CityHsinchu
    Period13/4/2213/4/24

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    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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