An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application

Tohru Furuyama, Takashi Ohsawa, Yohji Watanabe, Kazuyoshi Muraoka, Kenji Natori, Yousei Nagahama, Tohru Kimura, Hiroto Tanaka

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

A novel 2-bit (four-level)/cell storage technique is described. This technique saves the RAM area, in particular the cell array area which is highly defect sensitive provides fairly fast access time. An experimental 1-Mbit DRAM has been fabricated and has successfully demon-strated the feasibility of this technique for embedded memory applications.

Original languageEnglish
Pages (from-to)388-393
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume24
Issue number2
DOIs
Publication statusPublished - 1989
Externally publishedYes

Fingerprint

Dynamic random access storage
Random access storage
Data storage equipment
Defects

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Furuyama, T., Ohsawa, T., Watanabe, Y., Muraoka, K., Natori, K., Nagahama, Y., ... Tanaka, H. (1989). An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application. IEEE Journal of Solid-State Circuits, 24(2), 388-393. https://doi.org/10.1109/4.18599

An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application. / Furuyama, Tohru; Ohsawa, Takashi; Watanabe, Yohji; Muraoka, Kazuyoshi; Natori, Kenji; Nagahama, Yousei; Kimura, Tohru; Tanaka, Hiroto.

In: IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, 1989, p. 388-393.

Research output: Contribution to journalArticle

Furuyama, T, Ohsawa, T, Watanabe, Y, Muraoka, K, Natori, K, Nagahama, Y, Kimura, T & Tanaka, H 1989, 'An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application', IEEE Journal of Solid-State Circuits, vol. 24, no. 2, pp. 388-393. https://doi.org/10.1109/4.18599
Furuyama, Tohru ; Ohsawa, Takashi ; Watanabe, Yohji ; Muraoka, Kazuyoshi ; Natori, Kenji ; Nagahama, Yousei ; Kimura, Tohru ; Tanaka, Hiroto. / An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application. In: IEEE Journal of Solid-State Circuits. 1989 ; Vol. 24, No. 2. pp. 388-393.
@article{6d67c887fa2c47caa1cef098334b02f8,
title = "An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application",
abstract = "A novel 2-bit (four-level)/cell storage technique is described. This technique saves the RAM area, in particular the cell array area which is highly defect sensitive provides fairly fast access time. An experimental 1-Mbit DRAM has been fabricated and has successfully demon-strated the feasibility of this technique for embedded memory applications.",
author = "Tohru Furuyama and Takashi Ohsawa and Yohji Watanabe and Kazuyoshi Muraoka and Kenji Natori and Yousei Nagahama and Tohru Kimura and Hiroto Tanaka",
year = "1989",
doi = "10.1109/4.18599",
language = "English",
volume = "24",
pages = "388--393",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",

}

TY - JOUR

T1 - An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application

AU - Furuyama, Tohru

AU - Ohsawa, Takashi

AU - Watanabe, Yohji

AU - Muraoka, Kazuyoshi

AU - Natori, Kenji

AU - Nagahama, Yousei

AU - Kimura, Tohru

AU - Tanaka, Hiroto

PY - 1989

Y1 - 1989

N2 - A novel 2-bit (four-level)/cell storage technique is described. This technique saves the RAM area, in particular the cell array area which is highly defect sensitive provides fairly fast access time. An experimental 1-Mbit DRAM has been fabricated and has successfully demon-strated the feasibility of this technique for embedded memory applications.

AB - A novel 2-bit (four-level)/cell storage technique is described. This technique saves the RAM area, in particular the cell array area which is highly defect sensitive provides fairly fast access time. An experimental 1-Mbit DRAM has been fabricated and has successfully demon-strated the feasibility of this technique for embedded memory applications.

UR - http://www.scopus.com/inward/record.url?scp=0024648299&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024648299&partnerID=8YFLogxK

U2 - 10.1109/4.18599

DO - 10.1109/4.18599

M3 - Article

AN - SCOPUS:0024648299

VL - 24

SP - 388

EP - 393

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 2

ER -