An Experimental 4-Mbit CMOS DRAM

Tohru Furuyama, Takashi Ohsawa, Yohji Watanabe, Hidemi Ishiuchi, Toshiharu Watanabe, Takeshi Tanaka, Kenji Natori, Osamu Ozawa

Research output: Contribution to journalArticle

24 Citations (Scopus)

Abstract

A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.

Original languageEnglish
Pages (from-to)605-611
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume21
Issue number5
DOIs
Publication statusPublished - 1986
Externally publishedYes

Fingerprint

Dynamic random access storage
Random access storage
Masks
Hot carriers
Capacitors
Data storage equipment
Networks (circuits)
Electric potential
Metals
Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Furuyama, T., Ohsawa, T., Watanabe, Y., Ishiuchi, H., Watanabe, T., Tanaka, T., ... Ozawa, O. (1986). An Experimental 4-Mbit CMOS DRAM. IEEE Journal of Solid-State Circuits, 21(5), 605-611. https://doi.org/10.1109/JSSC.1986.1052584

An Experimental 4-Mbit CMOS DRAM. / Furuyama, Tohru; Ohsawa, Takashi; Watanabe, Yohji; Ishiuchi, Hidemi; Watanabe, Toshiharu; Tanaka, Takeshi; Natori, Kenji; Ozawa, Osamu.

In: IEEE Journal of Solid-State Circuits, Vol. 21, No. 5, 1986, p. 605-611.

Research output: Contribution to journalArticle

Furuyama, T, Ohsawa, T, Watanabe, Y, Ishiuchi, H, Watanabe, T, Tanaka, T, Natori, K & Ozawa, O 1986, 'An Experimental 4-Mbit CMOS DRAM', IEEE Journal of Solid-State Circuits, vol. 21, no. 5, pp. 605-611. https://doi.org/10.1109/JSSC.1986.1052584
Furuyama T, Ohsawa T, Watanabe Y, Ishiuchi H, Watanabe T, Tanaka T et al. An Experimental 4-Mbit CMOS DRAM. IEEE Journal of Solid-State Circuits. 1986;21(5):605-611. https://doi.org/10.1109/JSSC.1986.1052584
Furuyama, Tohru ; Ohsawa, Takashi ; Watanabe, Yohji ; Ishiuchi, Hidemi ; Watanabe, Toshiharu ; Tanaka, Takeshi ; Natori, Kenji ; Ozawa, Osamu. / An Experimental 4-Mbit CMOS DRAM. In: IEEE Journal of Solid-State Circuits. 1986 ; Vol. 21, No. 5. pp. 605-611.
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