An FPGA-based 4K UHDTV H.264/AVC video decoder

Yue Pan, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    An FPGA design of 4K UHDTV (Ultra-high definition TV) H.264 video decoder is proposed in this paper. The decoder is a complete one starting from bit stream input to decoding and final displaying, all of which are implemented on FPGA. Decoder engine that saves 51% DRAM bandwidth and display frame buffer addressing scheme that increases DRAM efficiency by 45% are proposed. The proposed work is capable of decoding and displaying a 3840×2160@30fps video in real time by 2 Altera Stratix III EP3SL150 DE3 FPGA boards (video decoding uses only one board) and four 1080p HDMI daughter boards. In this paper, the system structure, the FPGA configuration scheme, and particular designs targeting DRAM access efficiency are described. Besides, main specifications of the design and also the final performance are reported.

    Original languageEnglish
    Title of host publicationElectronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013
    DOIs
    Publication statusPublished - 2013
    Event2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013 - San Jose, CA
    Duration: 2013 Jul 152013 Jul 19

    Other

    Other2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013
    CitySan Jose, CA
    Period13/7/1513/7/19

    Fingerprint

    Field programmable gate arrays (FPGA)
    Dynamic random access storage
    Decoding
    Display devices
    Engines
    Specifications
    Bandwidth

    Keywords

    • 4K UHDTV
    • DRAM bandwidth
    • FPGA
    • H.264/AVC
    • HDMI displaying
    • video decoder

    ASJC Scopus subject areas

    • Computer Graphics and Computer-Aided Design
    • Computer Vision and Pattern Recognition

    Cite this

    Pan, Y., Zhou, D., & Goto, S. (2013). An FPGA-based 4K UHDTV H.264/AVC video decoder. In Electronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013 [6618319] https://doi.org/10.1109/ICMEW.2013.6618319

    An FPGA-based 4K UHDTV H.264/AVC video decoder. / Pan, Yue; Zhou, Dajiang; Goto, Satoshi.

    Electronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013. 2013. 6618319.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Pan, Y, Zhou, D & Goto, S 2013, An FPGA-based 4K UHDTV H.264/AVC video decoder. in Electronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013., 6618319, 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013, San Jose, CA, 13/7/15. https://doi.org/10.1109/ICMEW.2013.6618319
    Pan Y, Zhou D, Goto S. An FPGA-based 4K UHDTV H.264/AVC video decoder. In Electronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013. 2013. 6618319 https://doi.org/10.1109/ICMEW.2013.6618319
    Pan, Yue ; Zhou, Dajiang ; Goto, Satoshi. / An FPGA-based 4K UHDTV H.264/AVC video decoder. Electronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013. 2013.
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