An FPGA-based 4K UHDTV H.264/AVC video decoder

Yue Pan; Dajiang Zhou; Satoshi Goto

doi:10.1109/ICMEW.2013.6618319

An FPGA-based 4K UHDTV H.264/AVC video decoder

Yue Pan, Dajiang Zhou, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

An FPGA design of 4K UHDTV (Ultra-high definition TV) H.264 video decoder is proposed in this paper. The decoder is a complete one starting from bit stream input to decoding and final displaying, all of which are implemented on FPGA. Decoder engine that saves 51% DRAM bandwidth and display frame buffer addressing scheme that increases DRAM efficiency by 45% are proposed. The proposed work is capable of decoding and displaying a 3840×2160@30fps video in real time by 2 Altera Stratix III EP3SL150 DE3 FPGA boards (video decoding uses only one board) and four 1080p HDMI daughter boards. In this paper, the system structure, the FPGA configuration scheme, and particular designs targeting DRAM access efficiency are described. Besides, main specifications of the design and also the final performance are reported.

Original language	English
Title of host publication	Electronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013
DOIs	https://doi.org/10.1109/ICMEW.2013.6618319
Publication status	Published - 2013
Event	2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013 - San Jose, CA Duration: 2013 Jul 15 → 2013 Jul 19

Other

Other	2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013
City	San Jose, CA
Period	13/7/15 → 13/7/19

Keywords

4K UHDTV
DRAM bandwidth
FPGA
H.264/AVC
HDMI displaying
video decoder

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Computer Vision and Pattern Recognition

Access to Document

10.1109/ICMEW.2013.6618319

Cite this

@inproceedings{74b0f38a33ce453585b9ee491c6ea93f,

title = "An FPGA-based 4K UHDTV H.264/AVC video decoder",

abstract = "An FPGA design of 4K UHDTV (Ultra-high definition TV) H.264 video decoder is proposed in this paper. The decoder is a complete one starting from bit stream input to decoding and final displaying, all of which are implemented on FPGA. Decoder engine that saves 51% DRAM bandwidth and display frame buffer addressing scheme that increases DRAM efficiency by 45% are proposed. The proposed work is capable of decoding and displaying a 3840×2160@30fps video in real time by 2 Altera Stratix III EP3SL150 DE3 FPGA boards (video decoding uses only one board) and four 1080p HDMI daughter boards. In this paper, the system structure, the FPGA configuration scheme, and particular designs targeting DRAM access efficiency are described. Besides, main specifications of the design and also the final performance are reported.",

keywords = "4K UHDTV, DRAM bandwidth, FPGA, H.264/AVC, HDMI displaying, video decoder",

author = "Yue Pan and Dajiang Zhou and Satoshi Goto",

year = "2013",

doi = "10.1109/ICMEW.2013.6618319",

language = "English",

isbn = "9781479916047",

booktitle = "Electronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013",

note = "2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013 ; Conference date: 15-07-2013 Through 19-07-2013",

}

TY - GEN

T1 - An FPGA-based 4K UHDTV H.264/AVC video decoder

AU - Pan, Yue

AU - Zhou, Dajiang

AU - Goto, Satoshi

PY - 2013

Y1 - 2013

N2 - An FPGA design of 4K UHDTV (Ultra-high definition TV) H.264 video decoder is proposed in this paper. The decoder is a complete one starting from bit stream input to decoding and final displaying, all of which are implemented on FPGA. Decoder engine that saves 51% DRAM bandwidth and display frame buffer addressing scheme that increases DRAM efficiency by 45% are proposed. The proposed work is capable of decoding and displaying a 3840×2160@30fps video in real time by 2 Altera Stratix III EP3SL150 DE3 FPGA boards (video decoding uses only one board) and four 1080p HDMI daughter boards. In this paper, the system structure, the FPGA configuration scheme, and particular designs targeting DRAM access efficiency are described. Besides, main specifications of the design and also the final performance are reported.

AB - An FPGA design of 4K UHDTV (Ultra-high definition TV) H.264 video decoder is proposed in this paper. The decoder is a complete one starting from bit stream input to decoding and final displaying, all of which are implemented on FPGA. Decoder engine that saves 51% DRAM bandwidth and display frame buffer addressing scheme that increases DRAM efficiency by 45% are proposed. The proposed work is capable of decoding and displaying a 3840×2160@30fps video in real time by 2 Altera Stratix III EP3SL150 DE3 FPGA boards (video decoding uses only one board) and four 1080p HDMI daughter boards. In this paper, the system structure, the FPGA configuration scheme, and particular designs targeting DRAM access efficiency are described. Besides, main specifications of the design and also the final performance are reported.

KW - 4K UHDTV

KW - DRAM bandwidth

KW - FPGA

KW - H.264/AVC

KW - HDMI displaying

KW - video decoder

UR - http://www.scopus.com/inward/record.url?scp=84888209712&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84888209712&partnerID=8YFLogxK

U2 - 10.1109/ICMEW.2013.6618319

DO - 10.1109/ICMEW.2013.6618319

M3 - Conference contribution

AN - SCOPUS:84888209712

SN - 9781479916047

BT - Electronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013

T2 - 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013

Y2 - 15 July 2013 through 19 July 2013

ER -

An FPGA-based 4K UHDTV H.264/AVC video decoder

Abstract

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Keywords

ASJC Scopus subject areas

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