An FPGA implementation method based on distributed-register architectures

Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

Research output: Contribution to journalArticle

Abstract

In order to reduce the effects of interconnection delays in recent FPGA chips, circuit designs based on distributed-register architectures (which we call DR-based circuit designs) are important. Several methods for DR-based circuit designs have been proposed, where high-level synthesis techniques are effectively utilized. However, no methods have been proposed yet to practically implement DR-based circuits on FPGA chips. In this paper, we propose an FPGA implementation method based on DR architectures and apply it to a DR-based circuit. The implementation result shows that it operates on an FPGA chip with 21% faster than the circuit based on a traditional architecture.

Original languageEnglish
Pages (from-to)38-41
Number of pages4
JournalIPSJ Transactions on System LSI Design Methodology
Volume12
DOIs
Publication statusPublished - 2019 Feb 1

Keywords

  • Distributed-register architecture
  • FPGA implementation
  • High-level synthesis
  • Interconnection delay

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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