An interactive simulation system for structured logic design - ISS

Takeshi Sakai; Yoshiyuki Tsuchida; Hiroto Yasuura; Yasushi Ooi; Yoshitsugu Ono; Hlroshi Kano; Shinji Kimura; Shuzo Yajima

doi:10.1109/DAC.1982.1585579

An interactive simulation system for structured logic design - ISS

Takeshi Sakai, Yoshiyuki Tsuchida, Hiroto Yasuura, Yasushi Ooi, Yoshitsugu Ono, Hlroshi Kano, Shinji Kimura, Shuzo Yajima

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

An Interactive Simulation System (ISS) is presented. ISS is an integrated interactive CAD system for logic design, and is configurated "module oriented" to support structured logic design. An Interactive Simulator (IS) is used for design verification. A designer can control simulation steps interactively in IS, and he can find design errors early using a good interactive interface. A Structured Hardware Design Language (SHDL) is used to describe logic designs.

Original language	English
Pages (from-to)	747-754
Number of pages	8
Journal	Proceedings - Design Automation Conference
DOIs	https://doi.org/10.1109/DAC.1982.1585579
Publication status	Published - 1982 Jan 1
Externally published	Yes
Event	19th Design Automation Conference, DAC 1982 - Las Vegas, United States Duration: 1982 Jun 14 → 1982 Jun 16

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modelling and Simulation

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10.1109/DAC.1982.1585579

Cite this

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title = "An interactive simulation system for structured logic design - ISS",

abstract = "An Interactive Simulation System (ISS) is presented. ISS is an integrated interactive CAD system for logic design, and is configurated {"}module oriented{"} to support structured logic design. An Interactive Simulator (IS) is used for design verification. A designer can control simulation steps interactively in IS, and he can find design errors early using a good interactive interface. A Structured Hardware Design Language (SHDL) is used to describe logic designs.",

author = "Takeshi Sakai and Yoshiyuki Tsuchida and Hiroto Yasuura and Yasushi Ooi and Yoshitsugu Ono and Hlroshi Kano and Shinji Kimura and Shuzo Yajima",

note = "Funding Information: The authors would like to express their sincere appliciation to Associate Professor Y.Kambayashi, Mr. H.Hiraishi and Dr. K. Inagaki of Kyoto University for their many helpful suggestions and discussions. The authors are also indebted to Mr. H.Oohira for the implementation of the input pattern translator. This work is partly supported by the Science Foundation Grant of the Ministry of Education of Japan. Publisher Copyright: {\textcopyright} 1982 IEEE.; 19th Design Automation Conference, DAC 1982 ; Conference date: 14-06-1982 Through 16-06-1982",

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AU - Sakai, Takeshi

AU - Tsuchida, Yoshiyuki

AU - Yasuura, Hiroto

AU - Ooi, Yasushi

AU - Ono, Yoshitsugu

AU - Kano, Hlroshi

AU - Kimura, Shinji

AU - Yajima, Shuzo

N1 - Funding Information: The authors would like to express their sincere appliciation to Associate Professor Y.Kambayashi, Mr. H.Hiraishi and Dr. K. Inagaki of Kyoto University for their many helpful suggestions and discussions. The authors are also indebted to Mr. H.Oohira for the implementation of the input pattern translator. This work is partly supported by the Science Foundation Grant of the Ministry of Education of Japan. Publisher Copyright: © 1982 IEEE.

PY - 1982/1/1

Y1 - 1982/1/1

N2 - An Interactive Simulation System (ISS) is presented. ISS is an integrated interactive CAD system for logic design, and is configurated "module oriented" to support structured logic design. An Interactive Simulator (IS) is used for design verification. A designer can control simulation steps interactively in IS, and he can find design errors early using a good interactive interface. A Structured Hardware Design Language (SHDL) is used to describe logic designs.

AB - An Interactive Simulation System (ISS) is presented. ISS is an integrated interactive CAD system for logic design, and is configurated "module oriented" to support structured logic design. An Interactive Simulator (IS) is used for design verification. A designer can control simulation steps interactively in IS, and he can find design errors early using a good interactive interface. A Structured Hardware Design Language (SHDL) is used to describe logic designs.

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An interactive simulation system for structured logic design - ISS

Abstract

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