An l1 cache design space exploration system for embedded applications

Nobuaki Tojo*, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


In an embedded system where a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: the number of sets, a line size, and an associativity. In this paper, we first propose two cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but decrease the number of cache hit/miss judgments dramatically. We further propose three more cache design space exploration algorithms: CRMF1, CRMF2, and CRMF3, based on our experimental observations. They can find an almost optimal cache configuration from the viewpoint of access time. By using our approach, the number of cache hit/miss judgments required for optimizing cache configurations is reduced to 1/10-1/50 compared to conventional approaches. As a result, our proposed approach totally runs an average of 3.2 times faster and a maximum of 5.3 times faster compared to the fastest approach proposed so far. Our proposed cache simulation approach achieves the world fastest cache design space exploration when optimizing total memory access time.

Original languageEnglish
Pages (from-to)1442-1453
Number of pages12
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number6
Publication statusPublished - 2009 Jan 1


  • Cache
  • Cache optimization
  • Cache simulation
  • Design space exploration
  • Embedded system

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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