A 4.2-µm2 stacked capacitor DRAM cell is achieved using conventional i-line photolithography that realizes 0.6-µm pattern delineation. In order to obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film are developed. These new technologies enable a stored charge of 25 fF/bit (41 fC/bit) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mbit DRAM’s.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials