An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell

Shin Ichiro Kimura, Yoshifumi Kawamoto, Norio Hasegawa, Atsushi Hiraiwa, Yoshinobu Nakagome, Masakazu Aoki, Hideo Sunami, Kiyoo Itoh, Teruaki Kisu

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A 4.2-µm2 stacked capacitor DRAM cell is achieved using conventional i-line photolithography that realizes 0.6-µm pattern delineation. In order to obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film are developed. These new technologies enable a stored charge of 25 fF/bit (41 fC/bit) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mbit DRAM’s.

Original languageEnglish
Pages (from-to)1591-1595
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume35
Issue number10
DOIs
Publication statusPublished - 1988
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Fingerprint Dive into the research topics of 'An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell'. Together they form a unique fingerprint.

  • Cite this

    Kimura, S. I., Kawamoto, Y., Hasegawa, N., Hiraiwa, A., Nakagome, Y., Aoki, M., Sunami, H., Itoh, K., & Kisu, T. (1988). An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell. IEEE Transactions on Electron Devices, 35(10), 1591-1595. https://doi.org/10.1109/16.7358