An SDRAM controller optimized for high definition video coding application

Jiayi Zhu; Peilin Liu; Dajiang Zhou

doi:10.1109/ISCAS.2008.4542218

An SDRAM controller optimized for high definition video coding application

Jiayi Zhu, Peilin Liu, Dajiang Zhou

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

32 Citations (Scopus)

Abstract

The huge SDRAM bandwidth requirement is an architectural bottleneck of video decoders. Besides the large amounts of data transmission cycles, many extra overhead (up to over 50%) are incurred by the ACTIVE or PRECHARGE (A\P) operations in conventional SDRAM controllers. In this paper, we propose an optimized SDRAM controller, which can improve the bandwidth efficiency by eliminating most of the extra overhead. An access management scheme that enables consecutive data transmission is employed to reduce the need of A\P operations. In addition, a scheduler is designed to hide the latency for A\P operations. Experimental result shows that the SDRAM controller is able to meet the bandwidth requirement of real-time decoding 1080P H.264 video streams, at less than 100Mhz with 32-bit DDR SDRAM.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Pages	3518-3521
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2008.4542218
Publication status	Published - 2008
Externally published	Yes
Event	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA Duration: 2008 May 18 → 2008 May 21

Other

Other	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
City	Seattle, WA
Period	08/5/18 → 08/5/21

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2008.4542218

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Cite this

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abstract = "The huge SDRAM bandwidth requirement is an architectural bottleneck of video decoders. Besides the large amounts of data transmission cycles, many extra overhead (up to over 50%) are incurred by the ACTIVE or PRECHARGE (A\P) operations in conventional SDRAM controllers. In this paper, we propose an optimized SDRAM controller, which can improve the bandwidth efficiency by eliminating most of the extra overhead. An access management scheme that enables consecutive data transmission is employed to reduce the need of A\P operations. In addition, a scheduler is designed to hide the latency for A\P operations. Experimental result shows that the SDRAM controller is able to meet the bandwidth requirement of real-time decoding 1080P H.264 video streams, at less than 100Mhz with 32-bit DDR SDRAM.",

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language = "English",

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AU - Liu, Peilin

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AB - The huge SDRAM bandwidth requirement is an architectural bottleneck of video decoders. Besides the large amounts of data transmission cycles, many extra overhead (up to over 50%) are incurred by the ACTIVE or PRECHARGE (A\P) operations in conventional SDRAM controllers. In this paper, we propose an optimized SDRAM controller, which can improve the bandwidth efficiency by eliminating most of the extra overhead. An access management scheme that enables consecutive data transmission is employed to reduce the need of A\P operations. In addition, a scheduler is designed to hide the latency for A\P operations. Experimental result shows that the SDRAM controller is able to meet the bandwidth requirement of real-time decoding 1080P H.264 video streams, at less than 100Mhz with 32-bit DDR SDRAM.

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