An SoC based HW/SW co-design architecture for multi-standard audio decoding

Dajiang Zhou, Peilin Liu, Ji Kong, Yunfei Zhang, Bin He, Ning Deng

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

In this paper, we presented an SOC based HW/SW co-design architecture for multi-standard audio decoding. It is developed to support the audio standards of AAC LC profile, Dolby AC3, Ogg Vorbis, MPEG-1 Layer 3 (MP3) and Windows Media Audio (WMA). A VLSI reconfigurable filterbank based on CORDIC algorithm is developed to accelerate the multistandard decoding process. We designed and implemented an SOC platform to verify the filterbank as an IP core. Experimental result shows that the architecture is able to perform real-time audio decoding at low frequency (typically 10.6MHz for AAC and 11.3MHz for MP3) and the implementation cost is low (44.3k gates, 34k bytes RAM and 45k bytes data ROM for 5 audio standards). The architecture is also flexible for extending support of new formats and standards.

Original languageEnglish
Title of host publication2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages200-203
Number of pages4
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju
Duration: 2007 Nov 122007 Nov 14

Other

Other2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
CityJeju
Period07/11/1207/11/14

Fingerprint

Decoding
ROM
Random access storage
System-on-chip
Costs

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Zhou, D., Liu, P., Kong, J., Zhang, Y., He, B., & Deng, N. (2007). An SoC based HW/SW co-design architecture for multi-standard audio decoding. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 200-203). [4425765] https://doi.org/10.1109/ASSCC.2007.4425765

An SoC based HW/SW co-design architecture for multi-standard audio decoding. / Zhou, Dajiang; Liu, Peilin; Kong, Ji; Zhang, Yunfei; He, Bin; Deng, Ning.

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC. 2007. p. 200-203 4425765.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhou, D, Liu, P, Kong, J, Zhang, Y, He, B & Deng, N 2007, An SoC based HW/SW co-design architecture for multi-standard audio decoding. in 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425765, pp. 200-203, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, 07/11/12. https://doi.org/10.1109/ASSCC.2007.4425765
Zhou D, Liu P, Kong J, Zhang Y, He B, Deng N. An SoC based HW/SW co-design architecture for multi-standard audio decoding. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC. 2007. p. 200-203. 4425765 https://doi.org/10.1109/ASSCC.2007.4425765
Zhou, Dajiang ; Liu, Peilin ; Kong, Ji ; Zhang, Yunfei ; He, Bin ; Deng, Ning. / An SoC based HW/SW co-design architecture for multi-standard audio decoding. 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC. 2007. pp. 200-203
@inproceedings{cfb129dfeb8e41c88c83df4db7d92b94,
title = "An SoC based HW/SW co-design architecture for multi-standard audio decoding",
abstract = "In this paper, we presented an SOC based HW/SW co-design architecture for multi-standard audio decoding. It is developed to support the audio standards of AAC LC profile, Dolby AC3, Ogg Vorbis, MPEG-1 Layer 3 (MP3) and Windows Media Audio (WMA). A VLSI reconfigurable filterbank based on CORDIC algorithm is developed to accelerate the multistandard decoding process. We designed and implemented an SOC platform to verify the filterbank as an IP core. Experimental result shows that the architecture is able to perform real-time audio decoding at low frequency (typically 10.6MHz for AAC and 11.3MHz for MP3) and the implementation cost is low (44.3k gates, 34k bytes RAM and 45k bytes data ROM for 5 audio standards). The architecture is also flexible for extending support of new formats and standards.",
author = "Dajiang Zhou and Peilin Liu and Ji Kong and Yunfei Zhang and Bin He and Ning Deng",
year = "2007",
doi = "10.1109/ASSCC.2007.4425765",
language = "English",
isbn = "1424413605",
pages = "200--203",
booktitle = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

}

TY - GEN

T1 - An SoC based HW/SW co-design architecture for multi-standard audio decoding

AU - Zhou, Dajiang

AU - Liu, Peilin

AU - Kong, Ji

AU - Zhang, Yunfei

AU - He, Bin

AU - Deng, Ning

PY - 2007

Y1 - 2007

N2 - In this paper, we presented an SOC based HW/SW co-design architecture for multi-standard audio decoding. It is developed to support the audio standards of AAC LC profile, Dolby AC3, Ogg Vorbis, MPEG-1 Layer 3 (MP3) and Windows Media Audio (WMA). A VLSI reconfigurable filterbank based on CORDIC algorithm is developed to accelerate the multistandard decoding process. We designed and implemented an SOC platform to verify the filterbank as an IP core. Experimental result shows that the architecture is able to perform real-time audio decoding at low frequency (typically 10.6MHz for AAC and 11.3MHz for MP3) and the implementation cost is low (44.3k gates, 34k bytes RAM and 45k bytes data ROM for 5 audio standards). The architecture is also flexible for extending support of new formats and standards.

AB - In this paper, we presented an SOC based HW/SW co-design architecture for multi-standard audio decoding. It is developed to support the audio standards of AAC LC profile, Dolby AC3, Ogg Vorbis, MPEG-1 Layer 3 (MP3) and Windows Media Audio (WMA). A VLSI reconfigurable filterbank based on CORDIC algorithm is developed to accelerate the multistandard decoding process. We designed and implemented an SOC platform to verify the filterbank as an IP core. Experimental result shows that the architecture is able to perform real-time audio decoding at low frequency (typically 10.6MHz for AAC and 11.3MHz for MP3) and the implementation cost is low (44.3k gates, 34k bytes RAM and 45k bytes data ROM for 5 audio standards). The architecture is also flexible for extending support of new formats and standards.

UR - http://www.scopus.com/inward/record.url?scp=51349124071&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=51349124071&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2007.4425765

DO - 10.1109/ASSCC.2007.4425765

M3 - Conference contribution

SN - 1424413605

SN - 9781424413607

SP - 200

EP - 203

BT - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

ER -