An ultra-low complexity motion estimation algorithm and its implementation of specific processor

Seiichiro Hiratsuka, Satoshi Goto, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to reduce its complexity. But they are still insufficient for embedded video coding systems. So we proposed an ultralow complexity ME algorithm that is suitable for the software implementation. The simulation results show that proposed algorithm has about 1,000 times the speedup than full search (FS) maintaining high image quality. And we also propose an application specific instruction-set processor (ASIP) for ME. It is based on a reduced instruction set computer (RISC) with sum of absolute difference (SAD) operation circuit. Our ME ASIP is implemented on FPGA. It is required about 3,313 logic elements (LEs) and its hardware scale is about quarter of the previous ME ASIP. This ME ASIP will make a significant contribution to the development of compact video coding systems.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages4691-4694
Number of pages4
Publication statusPublished - 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos
Duration: 2006 May 212006 May 24

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CityKos
Period06/5/2106/5/24

Fingerprint

Motion estimation
Image coding
Image quality
Field programmable gate arrays (FPGA)
Hardware
Networks (circuits)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Hiratsuka, S., Goto, S., & Ikenaga, T. (2006). An ultra-low complexity motion estimation algorithm and its implementation of specific processor. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 4691-4694). [1693677]

An ultra-low complexity motion estimation algorithm and its implementation of specific processor. / Hiratsuka, Seiichiro; Goto, Satoshi; Ikenaga, Takeshi.

Proceedings - IEEE International Symposium on Circuits and Systems. 2006. p. 4691-4694 1693677.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hiratsuka, S, Goto, S & Ikenaga, T 2006, An ultra-low complexity motion estimation algorithm and its implementation of specific processor. in Proceedings - IEEE International Symposium on Circuits and Systems., 1693677, pp. 4691-4694, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 06/5/21.
Hiratsuka S, Goto S, Ikenaga T. An ultra-low complexity motion estimation algorithm and its implementation of specific processor. In Proceedings - IEEE International Symposium on Circuits and Systems. 2006. p. 4691-4694. 1693677
Hiratsuka, Seiichiro ; Goto, Satoshi ; Ikenaga, Takeshi. / An ultra-low complexity motion estimation algorithm and its implementation of specific processor. Proceedings - IEEE International Symposium on Circuits and Systems. 2006. pp. 4691-4694
@inproceedings{f526f0f10be949d3a566b904b90aa8ee,
title = "An ultra-low complexity motion estimation algorithm and its implementation of specific processor",
abstract = "Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to reduce its complexity. But they are still insufficient for embedded video coding systems. So we proposed an ultralow complexity ME algorithm that is suitable for the software implementation. The simulation results show that proposed algorithm has about 1,000 times the speedup than full search (FS) maintaining high image quality. And we also propose an application specific instruction-set processor (ASIP) for ME. It is based on a reduced instruction set computer (RISC) with sum of absolute difference (SAD) operation circuit. Our ME ASIP is implemented on FPGA. It is required about 3,313 logic elements (LEs) and its hardware scale is about quarter of the previous ME ASIP. This ME ASIP will make a significant contribution to the development of compact video coding systems.",
author = "Seiichiro Hiratsuka and Satoshi Goto and Takeshi Ikenaga",
year = "2006",
language = "English",
isbn = "0780393902",
pages = "4691--4694",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

}

TY - GEN

T1 - An ultra-low complexity motion estimation algorithm and its implementation of specific processor

AU - Hiratsuka, Seiichiro

AU - Goto, Satoshi

AU - Ikenaga, Takeshi

PY - 2006

Y1 - 2006

N2 - Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to reduce its complexity. But they are still insufficient for embedded video coding systems. So we proposed an ultralow complexity ME algorithm that is suitable for the software implementation. The simulation results show that proposed algorithm has about 1,000 times the speedup than full search (FS) maintaining high image quality. And we also propose an application specific instruction-set processor (ASIP) for ME. It is based on a reduced instruction set computer (RISC) with sum of absolute difference (SAD) operation circuit. Our ME ASIP is implemented on FPGA. It is required about 3,313 logic elements (LEs) and its hardware scale is about quarter of the previous ME ASIP. This ME ASIP will make a significant contribution to the development of compact video coding systems.

AB - Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to reduce its complexity. But they are still insufficient for embedded video coding systems. So we proposed an ultralow complexity ME algorithm that is suitable for the software implementation. The simulation results show that proposed algorithm has about 1,000 times the speedup than full search (FS) maintaining high image quality. And we also propose an application specific instruction-set processor (ASIP) for ME. It is based on a reduced instruction set computer (RISC) with sum of absolute difference (SAD) operation circuit. Our ME ASIP is implemented on FPGA. It is required about 3,313 logic elements (LEs) and its hardware scale is about quarter of the previous ME ASIP. This ME ASIP will make a significant contribution to the development of compact video coding systems.

UR - http://www.scopus.com/inward/record.url?scp=34250816157&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34250816157&partnerID=8YFLogxK

M3 - Conference contribution

SN - 0780393902

SN - 9780780393905

SP - 4691

EP - 4694

BT - Proceedings - IEEE International Symposium on Circuits and Systems

ER -