An ultra-low-voltage Class-C PMOS VCO IC with PVT compensation in 180-nm CMOS

Xin Yang, Xiao Xu, Toshihiko Yoshimasu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

A novel 2.2-GHz-band ultra-low-voltage Class-C PMOS VCO IC with negative reference and amplitude feedback loop is proposed. The negative reference initially adapts a sufficient bias for the LC-VCO circuit to ensure a robust oscillation start-up. The feedback loop then adaptively controls the bias condition of LC-VCO for Class-C operation in steady-state. The reliability of the feedback loop is enhanced over PVT variation. The Class-C VCO IC has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of -113.2 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier frequency with a supply voltage of only 0.3 V.

Original languageEnglish
Title of host publicationSiRF 2016 - 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages107-109
Number of pages3
ISBN (Print)9781509016877
DOIs
Publication statusPublished - 2016 Mar 31
Event16th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2016 - Austin, United States
Duration: 2016 Jan 242016 Jan 27

Other

Other16th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2016
CountryUnited States
CityAustin
Period16/1/2416/1/27

Keywords

  • 180-nm CMOS
  • amplitude feedback loop
  • Class-C VCO
  • negative reference
  • PMOS
  • PVT compensation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Computer Networks and Communications

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