Abstract
A novel 2.2-GHz-band ultra-low-voltage Class-C PMOS VCO IC with negative reference and amplitude feedback loop is proposed. The negative reference initially adapts a sufficient bias for the LC-VCO circuit to ensure a robust oscillation start-up. The feedback loop then adaptively controls the bias condition of LC-VCO for Class-C operation in steady-state. The reliability of the feedback loop is enhanced over PVT variation. The Class-C VCO IC has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of -113.2 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier frequency with a supply voltage of only 0.3 V.
Original language | English |
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Title of host publication | SiRF 2016 - 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 107-109 |
Number of pages | 3 |
ISBN (Print) | 9781509016877 |
DOIs | |
Publication status | Published - 2016 Mar 31 |
Event | 16th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2016 - Austin, United States Duration: 2016 Jan 24 → 2016 Jan 27 |
Other
Other | 16th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2016 |
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Country | United States |
City | Austin |
Period | 16/1/24 → 16/1/27 |
Keywords
- 180-nm CMOS
- amplitude feedback loop
- Class-C VCO
- negative reference
- PMOS
- PVT compensation
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
- Computer Networks and Communications