An ultra-low-voltage Class-C PMOS VCO IC with PVT compensation in 180-nm CMOS

Xin Yang; Xiao Xu; Toshihiko Yoshimasu

doi:10.1109/SIRF.2016.7445482

An ultra-low-voltage Class-C PMOS VCO IC with PVT compensation in 180-nm CMOS

Xin Yang, Xiao Xu, Toshihiko Yoshimasu

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

A novel 2.2-GHz-band ultra-low-voltage Class-C PMOS VCO IC with negative reference and amplitude feedback loop is proposed. The negative reference initially adapts a sufficient bias for the LC-VCO circuit to ensure a robust oscillation start-up. The feedback loop then adaptively controls the bias condition of LC-VCO for Class-C operation in steady-state. The reliability of the feedback loop is enhanced over PVT variation. The Class-C VCO IC has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of -113.2 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier frequency with a supply voltage of only 0.3 V.

Original language	English
Title of host publication	SiRF 2016 - 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	107-109
Number of pages	3
ISBN (Print)	9781509016877
DOIs	https://doi.org/10.1109/SIRF.2016.7445482
Publication status	Published - 2016 Mar 31
Event	16th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2016 - Austin, United States Duration: 2016 Jan 24 → 2016 Jan 27

Other

Other	16th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2016
Country	United States
City	Austin
Period	16/1/24 → 16/1/27

Keywords

180-nm CMOS
amplitude feedback loop
Class-C VCO
negative reference
PMOS
PVT compensation

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Computer Networks and Communications

Access to Document

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Cite this

An ultra-low-voltage Class-C PMOS VCO IC with PVT compensation in 180-nm CMOS. / Yang, Xin; Xu, Xiao; Yoshimasu, Toshihiko.

SiRF 2016 - 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. Institute of Electrical and Electronics Engineers Inc., 2016. p. 107-109 7445482.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yang, X, Xu, X & Yoshimasu, T 2016, An ultra-low-voltage Class-C PMOS VCO IC with PVT compensation in 180-nm CMOS. in SiRF 2016 - 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems., 7445482, Institute of Electrical and Electronics Engineers Inc., pp. 107-109, 16th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2016, Austin, United States, 16/1/24. https://doi.org/10.1109/SIRF.2016.7445482

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keywords = "180-nm CMOS, amplitude feedback loop, Class-C VCO, negative reference, PMOS, PVT compensation",

author = "Xin Yang and Xiao Xu and Toshihiko Yoshimasu",

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N2 - A novel 2.2-GHz-band ultra-low-voltage Class-C PMOS VCO IC with negative reference and amplitude feedback loop is proposed. The negative reference initially adapts a sufficient bias for the LC-VCO circuit to ensure a robust oscillation start-up. The feedback loop then adaptively controls the bias condition of LC-VCO for Class-C operation in steady-state. The reliability of the feedback loop is enhanced over PVT variation. The Class-C VCO IC has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of -113.2 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier frequency with a supply voltage of only 0.3 V.

AB - A novel 2.2-GHz-band ultra-low-voltage Class-C PMOS VCO IC with negative reference and amplitude feedback loop is proposed. The negative reference initially adapts a sufficient bias for the LC-VCO circuit to ensure a robust oscillation start-up. The feedback loop then adaptively controls the bias condition of LC-VCO for Class-C operation in steady-state. The reliability of the feedback loop is enhanced over PVT variation. The Class-C VCO IC has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of -113.2 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier frequency with a supply voltage of only 0.3 V.

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