Analysis and reduction of SRAM PUF Bit Error Rate

Hirofumi Shinohara; Baikun Zheng; Yanhao Piao; Bo Liu; Shiyu Liu

doi:10.1109/VLSI-DAT.2017.7939688

Analysis and reduction of SRAM PUF Bit Error Rate

Hirofumi Shinohara, Baikun Zheng, Yanhao Piao, Bo Liu, Shiyu Liu

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.

Original language	English
Title of host publication	2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509039692
DOIs	https://doi.org/10.1109/VLSI-DAT.2017.7939688
Publication status	Published - 2017 Jun 5
Event	2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan, Province of China Duration: 2017 Apr 24 → 2017 Apr 27

Other

Other	2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	17/4/24 → 17/4/27

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/VLSI-DAT.2017.7939688

Cite this

Shinohara, H, Zheng, B, Piao, Y, Liu, B & Liu, S 2017, Analysis and reduction of SRAM PUF Bit Error Rate. in 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017., 7939688, Institute of Electrical and Electronics Engineers Inc., 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, Province of China, 17/4/24. https://doi.org/10.1109/VLSI-DAT.2017.7939688

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title = "Analysis and reduction of SRAM PUF Bit Error Rate",

abstract = "Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.",

author = "Hirofumi Shinohara and Baikun Zheng and Yanhao Piao and Bo Liu and Shiyu Liu",

year = "2017",

month = jun,

day = "5",

doi = "10.1109/VLSI-DAT.2017.7939688",

language = "English",

booktitle = "2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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note = "2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 ; Conference date: 24-04-2017 Through 27-04-2017",

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T1 - Analysis and reduction of SRAM PUF Bit Error Rate

AU - Shinohara, Hirofumi

AU - Zheng, Baikun

AU - Piao, Yanhao

AU - Liu, Bo

AU - Liu, Shiyu

PY - 2017/6/5

Y1 - 2017/6/5

N2 - Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.

AB - Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.

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U2 - 10.1109/VLSI-DAT.2017.7939688

DO - 10.1109/VLSI-DAT.2017.7939688

M3 - Conference contribution

AN - SCOPUS:85021446181

BT - 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

Y2 - 24 April 2017 through 27 April 2017

ER -

Analysis and reduction of SRAM PUF Bit Error Rate

Abstract

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