Analysis and reduction of SRAM PUF Bit Error Rate

Hirofumi Shinohara, Baikun Zheng, Yanhao Piao, Bo Liu, Shiyu Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.

Original languageEnglish
Title of host publication2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509039692
DOIs
Publication statusPublished - 2017 Jun 5
Event2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan, Province of China
Duration: 2017 Apr 242017 Apr 27

Other

Other2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
CountryTaiwan, Province of China
CityHsinchu
Period17/4/2417/4/27

Fingerprint

Static random access storage
Bit error rate
Transistors
Hardware security

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Shinohara, H., Zheng, B., Piao, Y., Liu, B., & Liu, S. (2017). Analysis and reduction of SRAM PUF Bit Error Rate. In 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 [7939688] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2017.7939688

Analysis and reduction of SRAM PUF Bit Error Rate. / Shinohara, Hirofumi; Zheng, Baikun; Piao, Yanhao; Liu, Bo; Liu, Shiyu.

2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7939688.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shinohara, H, Zheng, B, Piao, Y, Liu, B & Liu, S 2017, Analysis and reduction of SRAM PUF Bit Error Rate. in 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017., 7939688, Institute of Electrical and Electronics Engineers Inc., 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, Province of China, 17/4/24. https://doi.org/10.1109/VLSI-DAT.2017.7939688
Shinohara H, Zheng B, Piao Y, Liu B, Liu S. Analysis and reduction of SRAM PUF Bit Error Rate. In 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7939688 https://doi.org/10.1109/VLSI-DAT.2017.7939688
Shinohara, Hirofumi ; Zheng, Baikun ; Piao, Yanhao ; Liu, Bo ; Liu, Shiyu. / Analysis and reduction of SRAM PUF Bit Error Rate. 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 2017.
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