Abstract
Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.
| Original language | English |
|---|---|
| Title of host publication | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781509039692 |
| DOIs | |
| Publication status | Published - 2017 Jun 5 |
| Event | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan, Province of China Duration: 2017 Apr 24 → 2017 Apr 27 |
Other
| Other | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 |
|---|---|
| Country | Taiwan, Province of China |
| City | Hsinchu |
| Period | 17/4/24 → 17/4/27 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
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Cite this
Shinohara, H., Zheng, B., Piao, Y., Liu, B., & Liu, S. (2017). Analysis and reduction of SRAM PUF Bit Error Rate. In 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 [7939688] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2017.7939688