Analysis before starting an access: A new power-efficient instruction fetch mechanism

Jiongyao Ye, Yingtao Hu, Hongfeng Ding, Takahiro Watanabe

Research output: Contribution to journalArticle

Abstract

Power consumption has become an increasing concern in high performance microprocessor design. Especially, Instruction Cache (I-Cache) contributes a large portion of the total power consumption in a microprocessor, since it is a complex unit and is accessed very frequently. Several studies on low-power design have been presented for the powerefficient cache design. However, these techniques usually suffer from the restrictions in the traditional Instruction Fetch Unit (IFU) architectures where the fetch address needs to be sent to I-Cache once it is available. Therefore, work to reduce the power consumption is limited after the address generation and before starting an access. In this paper, we present a new power-aware IFU architecture, named Analysis Before Starting an Access (ABSA), which aims at maximizing the power efficiency of the lowpower designs by eliminating the restrictions on those low-power designs of the traditional IFU. To achieve this goal, ABSA reorganizes the IFU pipeline and carefully assigns tasks for each stages so that sufficient time and information can be provided for the low-power techniques to maximize the power efficiency before starting an access. The proposed design is fully scalable and its cost is low. Compared to a conventional IFU design, simulation results show that ABSA saves about 30.3% fetch power consumption, on average. I-Cache employed by ABSA reduces both static and dynamic power consumptions about 85.63% and 66.92%, respectively. Meanwhile the performance degradation is only about 0.97%.

Original languageEnglish
Pages (from-to)1398-1408
Number of pages11
JournalIEICE Transactions on Information and Systems
VolumeE94-D
Issue number7
DOIs
Publication statusPublished - 2011 Jul

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Electric power utilization
Microprocessor chips
Pipelines
Degradation
Costs

Keywords

  • Instruction cache
  • Instruction fetch mechanism
  • Low power

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Software
  • Artificial Intelligence
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition

Cite this

Analysis before starting an access : A new power-efficient instruction fetch mechanism. / Ye, Jiongyao; Hu, Yingtao; Ding, Hongfeng; Watanabe, Takahiro.

In: IEICE Transactions on Information and Systems, Vol. E94-D, No. 7, 07.2011, p. 1398-1408.

Research output: Contribution to journalArticle

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