Analysis of coupling noise between adjacent bit lines in megabit DRAM's

Yasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara

Research output: Contribution to journalArticle

33 Citations (Scopus)

Abstract

Different bit-line structures, bit-line materials, widths, spacings, and passivation materials were fabricated to analyze the effect of the coupling noise between adjacent bit lines in megabit DRAMs. Each component of total bit-line capacitance was measured to obtain the bit-line-to-bit-line capacitance and the other contributions to the total bit-line capacitance. Accelerated soft error tests were performed on each sample. The results suggest the existence of two types of noise effects. One is the READ-signal degradation just after the word-line rises. The other is the disturbance in sensing operation. The larger the ratio of the bit-line coupling capacitance to the other bit-line capacitance contributions is, the more serious both of the noise effects are. These noise mechanisms can be explained by the charge conservation model and the simulation of sensing operation. A polycide bit-line structure is less susceptible to these noises than an Al bit line because of its thickness and layer position.

Original languageEnglish
Pages (from-to)35-42
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume24
Issue number1
DOIs
Publication statusPublished - 1989 Feb
Externally publishedYes

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Dynamic random access storage
Capacitance
Passivation
Conservation
Degradation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Konishi, Y., Kumanoya, M., Yamasaki, H., Dosaka, K., & Yoshihara, T. (1989). Analysis of coupling noise between adjacent bit lines in megabit DRAM's. IEEE Journal of Solid-State Circuits, 24(1), 35-42. https://doi.org/10.1109/4.16299

Analysis of coupling noise between adjacent bit lines in megabit DRAM's. / Konishi, Yasuhiro; Kumanoya, Masaki; Yamasaki, Hiroyuki; Dosaka, Katsumi; Yoshihara, Tsutomu.

In: IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, 02.1989, p. 35-42.

Research output: Contribution to journalArticle

Konishi, Y, Kumanoya, M, Yamasaki, H, Dosaka, K & Yoshihara, T 1989, 'Analysis of coupling noise between adjacent bit lines in megabit DRAM's', IEEE Journal of Solid-State Circuits, vol. 24, no. 1, pp. 35-42. https://doi.org/10.1109/4.16299
Konishi, Yasuhiro ; Kumanoya, Masaki ; Yamasaki, Hiroyuki ; Dosaka, Katsumi ; Yoshihara, Tsutomu. / Analysis of coupling noise between adjacent bit lines in megabit DRAM's. In: IEEE Journal of Solid-State Circuits. 1989 ; Vol. 24, No. 1. pp. 35-42.
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