ANALYSIS OF PARASITIC RESISTANCE EFFECTS IN MOS LSI.

Kenji Anami, Masahiko Yoshimoto, Hirofumi Shinohara, Osamu Tomisawa, Takao Nakano

Research output: Contribution to journalArticle

Abstract

In this paper, from an analysis of the MOS transistor source and drain parasitic resistances a practical analytic equation is carried out which is compared with experimental results from MOS transistors. Next, the delay time in an MOS inverter is analyzed taking into account the interconnection resistance, solving a simplified practical analytic equation which also is compared with experiment.

Original languageEnglish
Pages (from-to)106-113
Number of pages8
JournalElectronics & communications in Japan
Volume66
Issue number10
Publication statusPublished - 1983 Oct
Externally publishedYes

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MOSFET devices
Time delay
Experiments

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Anami, K., Yoshimoto, M., Shinohara, H., Tomisawa, O., & Nakano, T. (1983). ANALYSIS OF PARASITIC RESISTANCE EFFECTS IN MOS LSI. Electronics & communications in Japan, 66(10), 106-113.

ANALYSIS OF PARASITIC RESISTANCE EFFECTS IN MOS LSI. / Anami, Kenji; Yoshimoto, Masahiko; Shinohara, Hirofumi; Tomisawa, Osamu; Nakano, Takao.

In: Electronics & communications in Japan, Vol. 66, No. 10, 10.1983, p. 106-113.

Research output: Contribution to journalArticle

Anami, K, Yoshimoto, M, Shinohara, H, Tomisawa, O & Nakano, T 1983, 'ANALYSIS OF PARASITIC RESISTANCE EFFECTS IN MOS LSI.', Electronics & communications in Japan, vol. 66, no. 10, pp. 106-113.
Anami K, Yoshimoto M, Shinohara H, Tomisawa O, Nakano T. ANALYSIS OF PARASITIC RESISTANCE EFFECTS IN MOS LSI. Electronics & communications in Japan. 1983 Oct;66(10):106-113.
Anami, Kenji ; Yoshimoto, Masahiko ; Shinohara, Hirofumi ; Tomisawa, Osamu ; Nakano, Takao. / ANALYSIS OF PARASITIC RESISTANCE EFFECTS IN MOS LSI. In: Electronics & communications in Japan. 1983 ; Vol. 66, No. 10. pp. 106-113.
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