Application-specific network-on-chip synthesis: Cluster generation and network component insertion

Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

Network-on-Chips (NoCs) have emerged as a paradigm for designing scalable communication architecture for System-on-Chips (SoCs). In NoC, one of the key challenges is to design the most power-performance efficient NoC topology that satisfies the application characteristics. In this paper, we present a three-stage synthesis approach to solve this problem. First, we propose an algorithm [floor-planning integrated with cluster generation (FCG)] to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Then, based on the size of applications, an Integer Linear Programming (ILP) and a heuristic method (H) are also proposed to place switches and network interfaces on the floorplan. Finally, a power and timing aware path allocation algorithm (PA) is carried out to determine the connectivity across different switches. Experimental results show that, for small applications, the NoC topology synthesized by FIP (FCGILPPA) method can save 27.54% of power, 4% of hop-count and 66% of running time on average. And for large applications, FHP (FCGHPA) synthesis method can even save 31.77% of power, 29% of hop-count and 94.18% of running time on average.

Original languageEnglish
Title of host publicationProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages144-149
Number of pages6
DOIs
Publication statusPublished - 2011
Event12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA
Duration: 2011 Mar 142011 Mar 16

Other

Other12th International Symposium on Quality Electronic Design, ISQED 2011
CitySanta Clara, CA
Period11/3/1411/3/16

Fingerprint

Network components
Switches
Topology
Heuristic methods
Linear programming
Interfaces (computer)
Electric power utilization
Planning
Network-on-chip
Communication

Keywords

  • floorplanning
  • networks on chips
  • topology synthesis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Zhong, W., Yu, B., Chen, S., Yoshimura, T., Dong, S., & Goto, S. (2011). Application-specific network-on-chip synthesis: Cluster generation and network component insertion. In Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011 (pp. 144-149). [5770718] https://doi.org/10.1109/ISQED.2011.5770718

Application-specific network-on-chip synthesis : Cluster generation and network component insertion. / Zhong, Wei; Yu, Bei; Chen, Song; Yoshimura, Takeshi; Dong, Sheqin; Goto, Satoshi.

Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011. 2011. p. 144-149 5770718.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhong, W, Yu, B, Chen, S, Yoshimura, T, Dong, S & Goto, S 2011, Application-specific network-on-chip synthesis: Cluster generation and network component insertion. in Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011., 5770718, pp. 144-149, 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, CA, 11/3/14. https://doi.org/10.1109/ISQED.2011.5770718
Zhong W, Yu B, Chen S, Yoshimura T, Dong S, Goto S. Application-specific network-on-chip synthesis: Cluster generation and network component insertion. In Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011. 2011. p. 144-149. 5770718 https://doi.org/10.1109/ISQED.2011.5770718
Zhong, Wei ; Yu, Bei ; Chen, Song ; Yoshimura, Takeshi ; Dong, Sheqin ; Goto, Satoshi. / Application-specific network-on-chip synthesis : Cluster generation and network component insertion. Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011. 2011. pp. 144-149
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