Application-specific network-on-chip synthesis with topology-aware floorplanning

Bo Huang; Song Chen; Wei Zhong; Takeshi Yoshimura

Application-specific network-on-chip synthesis with topology-aware floorplanning

Bo Huang, Song Chen, Wei Zhong, Takeshi Yoshimura

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

Application-Specific Network-on-Chip (ASNoC) architecture is more promising than regular network-on-Chip(NoC) for some particular applications. In ASNoC Design, one of the key challenges is to generate the most suitable and power efficient NoC topology. In previous works, the placement of the cores and network components, and the path allocation are explored separately. However, the path allocation strongly depends on the placement of cores and network components. In this paper, we integrate these steps together through the floorplanning with the cluster reconstruction and path allocation (FCRPA). Several SoC benchmarks have been tested and the results showed improvements over the latest works. copy;2012 IEEE.

Original language	English
Title of host publication	Proceedings - SBCCI 2012: 25th Symposium on Integrated Circuits and Systems Design
Publication status	Published - 2012
Event	2012 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012 - Brasilia Duration: 2012 Aug 30 → 2012 Sep 2

Other

Other	2012 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012
City	Brasilia
Period	12/8/30 → 12/9/2

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ASJC Scopus subject areas

Hardware and Architecture

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Huang, B., Chen, S., Zhong, W., & Yoshimura, T. (2012). Application-specific network-on-chip synthesis with topology-aware floorplanning. In Proceedings - SBCCI 2012: 25th Symposium on Integrated Circuits and Systems Design

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title = "Application-specific network-on-chip synthesis with topology-aware floorplanning",

abstract = "Application-Specific Network-on-Chip (ASNoC) architecture is more promising than regular network-on-Chip(NoC) for some particular applications. In ASNoC Design, one of the key challenges is to generate the most suitable and power efficient NoC topology. In previous works, the placement of the cores and network components, and the path allocation are explored separately. However, the path allocation strongly depends on the placement of cores and network components. In this paper, we integrate these steps together through the floorplanning with the cluster reconstruction and path allocation (FCRPA). Several SoC benchmarks have been tested and the results showed improvements over the latest works. copy;2012 IEEE.",

author = "Bo Huang and Song Chen and Wei Zhong and Takeshi Yoshimura",

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T1 - Application-specific network-on-chip synthesis with topology-aware floorplanning

AU - Huang, Bo

AU - Chen, Song

AU - Zhong, Wei

AU - Yoshimura, Takeshi

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N2 - Application-Specific Network-on-Chip (ASNoC) architecture is more promising than regular network-on-Chip(NoC) for some particular applications. In ASNoC Design, one of the key challenges is to generate the most suitable and power efficient NoC topology. In previous works, the placement of the cores and network components, and the path allocation are explored separately. However, the path allocation strongly depends on the placement of cores and network components. In this paper, we integrate these steps together through the floorplanning with the cluster reconstruction and path allocation (FCRPA). Several SoC benchmarks have been tested and the results showed improvements over the latest works. copy;2012 IEEE.

AB - Application-Specific Network-on-Chip (ASNoC) architecture is more promising than regular network-on-Chip(NoC) for some particular applications. In ASNoC Design, one of the key challenges is to generate the most suitable and power efficient NoC topology. In previous works, the placement of the cores and network components, and the path allocation are explored separately. However, the path allocation strongly depends on the placement of cores and network components. In this paper, we integrate these steps together through the floorplanning with the cluster reconstruction and path allocation (FCRPA). Several SoC benchmarks have been tested and the results showed improvements over the latest works. copy;2012 IEEE.

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M3 - Conference contribution

AN - SCOPUS:84870811689

SN - 9781467326087

BT - Proceedings - SBCCI 2012: 25th Symposium on Integrated Circuits and Systems Design

T2 - 2012 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012

Y2 - 30 August 2012 through 2 September 2012

ER -

Application-specific network-on-chip synthesis with topology-aware floorplanning

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