Abstract
Application-Specific Network-on-Chip (ASNoC) architecture is more promising than regular network-on-Chip(NoC) for some particular applications. In ASNoC Design, one of the key challenges is to generate the most suitable and power efficient NoC topology. In previous works, the placement of the cores and network components, and the path allocation are explored separately. However, the path allocation strongly depends on the placement of cores and network components. In this paper, we integrate these steps together through the floorplanning with the cluster reconstruction and path allocation (FCRPA). Several SoC benchmarks have been tested and the results showed improvements over the latest works. copy;2012 IEEE.
| Original language | English |
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| Title of host publication | Proceedings - SBCCI 2012: 25th Symposium on Integrated Circuits and Systems Design |
| Publication status | Published - 2012 |
| Event | 2012 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012 - Brasilia Duration: 2012 Aug 30 → 2012 Sep 2 |
Other
| Other | 2012 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012 |
|---|---|
| City | Brasilia |
| Period | 12/8/30 → 12/9/2 |
ASJC Scopus subject areas
- Hardware and Architecture
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Cite this
Huang, B., Chen, S., Zhong, W., & Yoshimura, T. (2012). Application-specific network-on-chip synthesis with topology-aware floorplanning. In Proceedings - SBCCI 2012: 25th Symposium on Integrated Circuits and Systems Design