Approaches to extra low voltage dram operation by soi-dram

Takahisa Eimori, Toshiyuki Oashi, Fukashi Morishita, Toshiaki Iwamatsu, Yasuo Yamaguchi, Fumihiro Okuda, Ke N.Ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Kazutami Arimoto, Yasuo Inoue, Shinji Komori, Masahide Inuishi, Tadashi Nishimura, Hirokazu Miyoshi

Research output: Contribution to journalArticlepeer-review

15 Citations (Scopus)


The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFET's with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFET's to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-μm 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.

Original languageEnglish
Pages (from-to)1000-1009
Number of pages10
JournalIEEE Transactions on Electron Devices
Issue number5
Publication statusPublished - 1998
Externally publishedYes


  • DRAM
  • High-speed circuits/devices
  • Silicon-oninsulator

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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