TY - GEN
T1 - Approximate multiplier using reordered 4-2 compressor with or-based error compensation
AU - Xu, Yufeng
AU - Guo, Yi
AU - Kimura, Shinji
N1 - Funding Information:
Thanks are due to members of Kimura laboratory in IPS of Waseda University for their discussions. This work was supported in part by JSPS KAKENHI Grant Number JP18H03217, and a fund from NEC.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - Today, the approximate circuits have become an efficient solution for low power design on human related error-tolerant applications, such as multimedia, recognition and several signal processing. Approximate multipliers are believed to be an important key to make approximate arithmetic systems, and more area efficient multiplier is expected. The paper proposes a new ar-ea-efficient 4-2 compressor based on input reordering and OR-based error compensation. By the reordering, we can focus on just 2 of 4 inputs, and the compressor becomes very simple and less gates. Two multipliers are proposed with different accuracy based on reordered compressors with OR-based error compensation. The experimental results show that the proposed multipliers achieve high accuracy (98.7% and 97.39%) while reduce power consumption (by 44.72% and 45.95%) and area (by 31.72% and 34.85%). The proposed approximate multipliers are applied on image sharpening process and show high PSNR and SSIM.
AB - Today, the approximate circuits have become an efficient solution for low power design on human related error-tolerant applications, such as multimedia, recognition and several signal processing. Approximate multipliers are believed to be an important key to make approximate arithmetic systems, and more area efficient multiplier is expected. The paper proposes a new ar-ea-efficient 4-2 compressor based on input reordering and OR-based error compensation. By the reordering, we can focus on just 2 of 4 inputs, and the compressor becomes very simple and less gates. Two multipliers are proposed with different accuracy based on reordered compressors with OR-based error compensation. The experimental results show that the proposed multipliers achieve high accuracy (98.7% and 97.39%) while reduce power consumption (by 44.72% and 45.95%) and area (by 31.72% and 34.85%). The proposed approximate multipliers are applied on image sharpening process and show high PSNR and SSIM.
KW - Approximate multiplier
KW - Compressor
KW - Energy and area efficiency
KW - Input reordering
KW - OR-based compensation
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U2 - 10.1109/ASICON47005.2019.8983625
DO - 10.1109/ASICON47005.2019.8983625
M3 - Conference contribution
AN - SCOPUS:85082608896
T3 - Proceedings of International Conference on ASIC
BT - Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019
A2 - Ye, Fan
A2 - Tang, Ting-Ao
PB - IEEE Computer Society
T2 - 13th IEEE International Conference on ASIC, ASICON 2019
Y2 - 29 October 2019 through 1 November 2019
ER -