Architecture of programmable systolic array processor for discrete wavelet transform

Jiro Miyake, Shigeo Kuninobu, Takaaki Baba

Research output: Contribution to journalArticle

Abstract

An architecture of a programmable systolic array processor is proposed for the discrete wavelet transform (DWT). This transform requires a huge amount of data to be filtered. To achieve this, many processor elements (PEs) are implemented. However, the hardware of a multiplier for multiply-accumulate operations is large, and complicated connections among PEs lower flexibility and scalability. By using the time-divided multiple-operation method, the execution unit with a simple structure of shifters and a three-input adder achieved 50% of hardware size and the same performance of that achieved with a multiplier and an adder. The unique network mechanism among PEs and the systolic array architecture provided a high level of data transfer, flexibility, and scalability. Using this architecture enables a processor with ten PEs to execute DWT for 1024×1024 image pixels in 26.3 ms.

Original languageEnglish
Pages (from-to)1853-1859
Number of pages7
JournalKyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers
Volume63
Issue number12
DOIs
Publication statusPublished - 2009 Dec

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Systolic arrays
Discrete wavelet transforms
Adders
Parallel processing systems
Scalability
Hardware
Data transfer
Pixels

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Media Technology
  • Computer Science Applications

Cite this

Architecture of programmable systolic array processor for discrete wavelet transform. / Miyake, Jiro; Kuninobu, Shigeo; Baba, Takaaki.

In: Kyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers, Vol. 63, No. 12, 12.2009, p. 1853-1859.

Research output: Contribution to journalArticle

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