Architecture optimization for H.264/AVC propagate partial SAD engine in HDTV application

Yiqing Huang, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents one compact propagate partial SAD (PPSAD) engine for H.264/AVC in HDTV application. Firstly, by using mode reduction technique, redundant registers in original PPSAD structure is removed. Secondly, circuit optimization is applied on the whole structure. Redundant adders within processing element (PE) and PE rows are removed. With TSMC 0.18um technology under worst case conditions (1.62V, 125°C), the proposed architecture can achieve 27.4% to 33.2% reduction of hardware and 11.7% saving in power consumption. When it is applied to parallel processing of HDTV 1080p real-time encoder, about 10k gates can be saved compared with previous design.

Original languageEnglish
Title of host publication2009 International SoC Design Conference, ISOCC 2009
Pages365-368
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
Duration: 2009 Nov 222009 Nov 24

Publication series

Name2009 International SoC Design Conference, ISOCC 2009

Conference

Conference2009 International SoC Design Conference, ISOCC 2009
CountryKorea, Republic of
CityBusan
Period09/11/2209/11/24

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Keywords

  • H.264/AVC
  • Hardware architecture
  • IME engine

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Huang, Y., & Ikenaga, T. (2009). Architecture optimization for H.264/AVC propagate partial SAD engine in HDTV application. In 2009 International SoC Design Conference, ISOCC 2009 (pp. 365-368). [5423841] (2009 International SoC Design Conference, ISOCC 2009). https://doi.org/10.1109/SOCDC.2009.5423841