Abstract
This paper presents one compact propagate partial SAD (PPSAD) engine for H.264/AVC in HDTV application. Firstly, by using mode reduction technique, redundant registers in original PPSAD structure is removed. Secondly, circuit optimization is applied on the whole structure. Redundant adders within processing element (PE) and PE rows are removed. With TSMC 0.18um technology under worst case conditions (1.62V, 125°C), the proposed architecture can achieve 27.4% to 33.2% reduction of hardware and 11.7% saving in power consumption. When it is applied to parallel processing of HDTV 1080p real-time encoder, about 10k gates can be saved compared with previous design.
| Original language | English |
|---|---|
| Title of host publication | 2009 International SoC Design Conference, ISOCC 2009 |
| Pages | 365-368 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2009 Dec 1 |
| Event | 2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of Duration: 2009 Nov 22 → 2009 Nov 24 |
Publication series
| Name | 2009 International SoC Design Conference, ISOCC 2009 |
|---|
Conference
| Conference | 2009 International SoC Design Conference, ISOCC 2009 |
|---|---|
| Country | Korea, Republic of |
| City | Busan |
| Period | 09/11/22 → 09/11/24 |
Keywords
- H.264/AVC
- Hardware architecture
- IME engine
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Cite this
Huang, Y., & Ikenaga, T. (2009). Architecture optimization for H.264/AVC propagate partial SAD engine in HDTV application. In 2009 International SoC Design Conference, ISOCC 2009 (pp. 365-368). [5423841] (2009 International SoC Design Conference, ISOCC 2009). https://doi.org/10.1109/SOCDC.2009.5423841