Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Nozomu Togawa, Yoshiharu Kataoka, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohsuki

    Research output: Contribution to journalArticle

    4 Citations (Scopus)

    Abstract

    Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2 ns when comparing estimated area and delay with logic-synthesized area and delay.

    Original languageEnglish
    Pages (from-to)2639-2647
    Number of pages9
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE84-A
    Issue number11
    Publication statusPublished - 2001 Nov

    Fingerprint

    Delay Estimation
    Digital Signal Processor
    Digital signal processors
    Hardware
    Software
    Hardware/software Partitioning
    Unit
    Critical Path
    kernel
    Application programs
    Software System

    Keywords

    • Area estimation
    • Delay estimation
    • Digital signal processor
    • Hardware/software cosynthesis
    • Micro processor

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

    Area and delay estimation in hardware/software cosynthesis for digital signal processor cores. / Togawa, Nozomu; Kataoka, Yoshiharu; Miyaoka, Yuichiro; Yanagisawa, Masao; Ohsuki, Tatsuo.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E84-A, No. 11, 11.2001, p. 2639-2647.

    Research output: Contribution to journalArticle

    @article{29bcd6bfd3cc4afbbcd9cff91de988d8,
    title = "Area and delay estimation in hardware/software cosynthesis for digital signal processor cores",
    abstract = "Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2{\%} and errors of delay estimation are less than 2 ns when comparing estimated area and delay with logic-synthesized area and delay.",
    keywords = "Area estimation, Delay estimation, Digital signal processor, Hardware/software cosynthesis, Micro processor",
    author = "Nozomu Togawa and Yoshiharu Kataoka and Yuichiro Miyaoka and Masao Yanagisawa and Tatsuo Ohsuki",
    year = "2001",
    month = "11",
    language = "English",
    volume = "E84-A",
    pages = "2639--2647",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "11",

    }

    TY - JOUR

    T1 - Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

    AU - Togawa, Nozomu

    AU - Kataoka, Yoshiharu

    AU - Miyaoka, Yuichiro

    AU - Yanagisawa, Masao

    AU - Ohsuki, Tatsuo

    PY - 2001/11

    Y1 - 2001/11

    N2 - Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2 ns when comparing estimated area and delay with logic-synthesized area and delay.

    AB - Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2 ns when comparing estimated area and delay with logic-synthesized area and delay.

    KW - Area estimation

    KW - Delay estimation

    KW - Digital signal processor

    KW - Hardware/software cosynthesis

    KW - Micro processor

    UR - http://www.scopus.com/inward/record.url?scp=0035518690&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0035518690&partnerID=8YFLogxK

    M3 - Article

    AN - SCOPUS:0035518690

    VL - E84-A

    SP - 2639

    EP - 2647

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 11

    ER -