Area/delay estimation for digital signal processor cores

Y. Miyaoka, Y. Kataoka, Nozomu Togawa, Masao Yanagisawa, T. Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)

    Abstract

    Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2ns when comparing estimated area and delay with logic-synthesized area and delay.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages156-161
    Number of pages6
    Volume2001-January
    ISBN (Print)0780366336
    DOIs
    Publication statusPublished - 2001
    EventAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
    Duration: 2001 Jan 302001 Feb 2

    Other

    OtherAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
    CountryJapan
    CityYokohama
    Period01/1/3001/2/2

      Fingerprint

    Keywords

    • Application software
    • Delay estimation
    • Digital signal processors
    • Equations
    • Estimation error
    • Hardware
    • Kernel
    • Registers
    • Signal synthesis
    • Software systems

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design

    Cite this

    Miyaoka, Y., Kataoka, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2001). Area/delay estimation for digital signal processor cores. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 2001-January, pp. 156-161). [913297] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2001.913297