ASIC CAD system based on hierarchical design-for-testability

Michiaki Emori*, Takashi Aikyo, Yasuhide Machida, Jun ichi Shikatani

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The authors propose a novel test CAD (computer-aided-design) system for ASIC (application-specific integrated circuits), including megacells which automatically insert high-testability logic. The strategy is to access megacells directly and independently. The overhead is only 2% to 3% of the total number of gates. With the proposed system, hierarchically designed logic data can be converted to high-testability logic. It is not necessary for the designers to have specialized knowledge about design-for-testability.

Original languageEnglish
Title of host publicationDigest of Papers - International Test Conference
PublisherPubl by IEEE
Pages404-409
Number of pages6
ISBN (Print)0818620641
Publication statusPublished - 1990 Sep
Externally publishedYes
EventProceedings - International Test Conference 1990 - Washington, DC, USA
Duration: 1990 Sep 101990 Sep 14

Publication series

NameDigest of Papers - International Test Conference
ISSN (Print)0743-1686

Conference

ConferenceProceedings - International Test Conference 1990
CityWashington, DC, USA
Period90/9/1090/9/14

ASJC Scopus subject areas

  • Engineering(all)

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