ATREX: Design for Testability System for Mega Gate LSIs

Michiaki Emori*, Junko Kumagai, Koichi Itaya, Takashi Aikyo, Tomoko Anan, Junichi Niimi

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some examples of circuit insertion which is supported by the system.

Original languageEnglish
Pages (from-to)126-129
Number of pages4
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 1997
Externally publishedYes
EventProceedings of the 1997 6th Asian Test Symposium - Akita, Jpn
Duration: 1997 Nov 171997 Nov 19

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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