AUTOMATIC COMPACTION METHOD FOR BUILDING BLOCK LSIS.

M. Ishikawa, T. Matsuda, Takeshi Yoshimura, S. Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The authors propose an automatic compaction method which minimizes the layout area for building block LSIs. A feature of this method is automatic wiring bend 'jog' insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that this method compresses the layout area to an amount only 1. 2-1. 5 times larger than that resulting from manual layout and therefore is very effective for achieving a minimum chip layout design. 8 refs.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Pages203-206
Number of pages4
Publication statusPublished - 1985
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Ishikawa, M., Matsuda, T., Yoshimura, T., & Goto, S. (1985). AUTOMATIC COMPACTION METHOD FOR BUILDING BLOCK LSIS. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 203-206). IEEE.