The authors propose an automatic compaction method which minimizes the layout area for building block LSIs. A feature of this method is automatic wiring bend 'jog' insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that this method compresses the layout area to an amount only 1. 2-1. 5 times larger than that resulting from manual layout and therefore is very effective for achieving a minimum chip layout design. 8 refs.
|Title of host publication||Proceedings - IEEE International Symposium on Circuits and Systems|
|Number of pages||4|
|Publication status||Published - 1985|
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials