Automatic layout synthesis for FIR filters using a silicon compiler

Masaki Ishikawa, Masato Edahiro, Takeshi Yoshimura, Takashi Miyazaki, Shin ichi Aikoh, Takao Nishitani, Kaoru Mitsuhashi, Mitsuhiro Furuichi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

A silicon compiler for finite impulse response (FIR) filters is presented. The synthesis system takes as inputs only filter specifications and processing word lengths, and generates the FIR filter mask patterns in a few minutes. The system consists of two programs: an FIR filter design program to determine FIR filter coefficients at the minimal filter order to meet design objectives, and a module generator to generate mask patterns according to optimal parameters obtained by the filter design program. For describing layout structures correctly and easily, the module generator provides graphical layout description tools, and includes mechanisms to permit designing the structures before leaf-cells are completed. Layouts for several filters which have been successfully generated in a short time are described. A system-generated single-chip VLSI chrominance-luminance separator for NTSC composite TV signals using four FIR filters is shown.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages2588-2591
Number of pages4
Volume4
Publication statusPublished - 1990
Externally publishedYes
Event1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
Duration: 1990 May 11990 May 3

Other

Other1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4)
CityNew Orleans, LA, USA
Period90/5/190/5/3

Fingerprint

FIR filters
Silicon
Masks
Word processing
Separators
Luminance
Specifications
Composite materials

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Ishikawa, M., Edahiro, M., Yoshimura, T., Miyazaki, T., Aikoh, S. I., Nishitani, T., ... Furuichi, M. (1990). Automatic layout synthesis for FIR filters using a silicon compiler. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 4, pp. 2588-2591). Publ by IEEE.

Automatic layout synthesis for FIR filters using a silicon compiler. / Ishikawa, Masaki; Edahiro, Masato; Yoshimura, Takeshi; Miyazaki, Takashi; Aikoh, Shin ichi; Nishitani, Takao; Mitsuhashi, Kaoru; Furuichi, Mitsuhiro.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4 Publ by IEEE, 1990. p. 2588-2591.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ishikawa, M, Edahiro, M, Yoshimura, T, Miyazaki, T, Aikoh, SI, Nishitani, T, Mitsuhashi, K & Furuichi, M 1990, Automatic layout synthesis for FIR filters using a silicon compiler. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 4, Publ by IEEE, pp. 2588-2591, 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4), New Orleans, LA, USA, 90/5/1.
Ishikawa M, Edahiro M, Yoshimura T, Miyazaki T, Aikoh SI, Nishitani T et al. Automatic layout synthesis for FIR filters using a silicon compiler. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4. Publ by IEEE. 1990. p. 2588-2591
Ishikawa, Masaki ; Edahiro, Masato ; Yoshimura, Takeshi ; Miyazaki, Takashi ; Aikoh, Shin ichi ; Nishitani, Takao ; Mitsuhashi, Kaoru ; Furuichi, Mitsuhiro. / Automatic layout synthesis for FIR filters using a silicon compiler. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4 Publ by IEEE, 1990. pp. 2588-2591
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