Automatic local memory management for multicores having global address space

Kouhei Yamamoto, Tomoya Shirakawa, Yoshitake Oki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    Embedded multicore processors for hard real-time applications like automobile engine control require the usage of local memory on each processor core to precisely meet the real-time deadline constraints, since cache memory cannot satisfy the deadline requirements due to cache misses. To utilize local memory, programmers or compilers need to explicitly manage data movement and data replacement for local memory considering the limited size. However, such management is extremely difficult and time consuming for programmers. This paper proposes an automatic local memory management method by compilers through (i) multi-dimensional data decomposition techniques to fit working sets onto limited size local memory (ii) suitable block management structures, called Adjustable Blocks, to create application specific fixed size data transfer blocks (iii) multi-dimensional templates to preserve the original multi-dimensional representations of the decomposed multi-dimensional data that are mapped onto one-dimensional Adjustable Blocks (iv) block replacement policies from liveness analysis of the decomposed data, and (v) code size reduction schemes to generate shorter codes. The proposed local memory management method is implemented on the OSCAR multigrain and multi-platform compiler and evaluated on the Renesas RP2 8 core embedded homogeneous multicore processor equipped with local and shared memory. Evaluations on 5 programs including multimedia and scientific applications show promising results. For instance, speedups on 8 cores compared to single core execution using off-chip shared memory on an AAC encoder program, a MPEG2 encoder program, Tomcatv, and Swim are improved from 7.14 to 20.12, 1.97 to 7.59, 5.73 to 7.38, and 7.40 to 11.30, respectively, when using local memory with the proposed method. These evaluations indicate the usefulness and the validity of the proposed local memory management method on real embedded multicore processors.

    Original languageEnglish
    Title of host publicationLanguages and Compilers for Parallel Computing - 29th International Workshop, LCPC 2016, Revised Papers
    PublisherSpringer Verlag
    Pages282-296
    Number of pages15
    Volume10136 LNCS
    ISBN (Print)9783319527086
    DOIs
    Publication statusPublished - 2017
    Event29th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2016 - Rochester, United States
    Duration: 2016 Sep 282016 Sep 30

    Publication series

    NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    Volume10136 LNCS
    ISSN (Print)03029743
    ISSN (Electronic)16113349

    Other

    Other29th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2016
    CountryUnited States
    CityRochester
    Period16/9/2816/9/30

    Keywords

    • Data decomposition
    • DMA
    • Global address space
    • Local memory management
    • Multicore
    • Parallelizing compiler

    ASJC Scopus subject areas

    • Theoretical Computer Science
    • Computer Science(all)

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  • Cite this

    Yamamoto, K., Shirakawa, T., Oki, Y., Yoshida, A., Kimura, K., & Kasahara, H. (2017). Automatic local memory management for multicores having global address space. In Languages and Compilers for Parallel Computing - 29th International Workshop, LCPC 2016, Revised Papers (Vol. 10136 LNCS, pp. 282-296). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 10136 LNCS). Springer Verlag. https://doi.org/10.1007/978-3-319-52709-3_21