Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip

Yuki Ando; Yukihito Ishida; Shinya Honda; Hiroaki Takada; Masato Edahiro

doi:10.1109/VLSI-SATA.2015.7050464

Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip

Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric by the high-bandwidth interconnect. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can realize various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by operating systems running on different types of processors. The problem is the cost to design and implement such communications. In order to overcome the problem and increase the design efficiency, we propose an automatic synthesis of inter-heterogeneous-processor communications from a general model description. The inter-heterogeneous-processor communications are realized using a shared memory and inter-processor interrupts. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs on the system with heterogeneous multiprocessors.

Original language	English
Title of host publication	2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479979264
DOIs	https://doi.org/10.1109/VLSI-SATA.2015.7050464
Publication status	Published - 2015 Feb 26
Externally published	Yes
Event	2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015 - Bengaluru, India Duration: 2015 Jan 8 → 2015 Jan 10

Publication series

Name	2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015

Conference

Conference	2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015
Country/Territory	India
City	Bengaluru
Period	15/1/8 → 15/1/10

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Computer Science Applications
Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-SATA.2015.7050464

Cite this

Ando, Y., Ishida, Y., Honda, S., Takada, H., & Edahiro, M. (2015). Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip. In 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015 [7050464] (2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-SATA.2015.7050464

Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip. / Ando, Yuki; Ishida, Yukihito; Honda, Shinya; Takada, Hiroaki; Edahiro, Masato.

2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7050464 (2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ando, Y, Ishida, Y, Honda, S, Takada, H & Edahiro, M 2015, Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip. in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015., 7050464, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, Institute of Electrical and Electronics Engineers Inc., 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, Bengaluru, India, 15/1/8. https://doi.org/10.1109/VLSI-SATA.2015.7050464

Ando Y, Ishida Y, Honda S, Takada H, Edahiro M. Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip. In 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7050464. (2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015). https://doi.org/10.1109/VLSI-SATA.2015.7050464

Ando, Yuki ; Ishida, Yukihito ; Honda, Shinya ; Takada, Hiroaki ; Edahiro, Masato. / Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip. 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015).

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abstract = "This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric by the high-bandwidth interconnect. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can realize various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by operating systems running on different types of processors. The problem is the cost to design and implement such communications. In order to overcome the problem and increase the design efficiency, we propose an automatic synthesis of inter-heterogeneous-processor communications from a general model description. The inter-heterogeneous-processor communications are realized using a shared memory and inter-processor interrupts. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs on the system with heterogeneous multiprocessors.",

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N2 - This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric by the high-bandwidth interconnect. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can realize various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by operating systems running on different types of processors. The problem is the cost to design and implement such communications. In order to overcome the problem and increase the design efficiency, we propose an automatic synthesis of inter-heterogeneous-processor communications from a general model description. The inter-heterogeneous-processor communications are realized using a shared memory and inter-processor interrupts. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs on the system with heterogeneous multiprocessors.

AB - This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric by the high-bandwidth interconnect. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can realize various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by operating systems running on different types of processors. The problem is the cost to design and implement such communications. In order to overcome the problem and increase the design efficiency, we propose an automatic synthesis of inter-heterogeneous-processor communications from a general model description. The inter-heterogeneous-processor communications are realized using a shared memory and inter-processor interrupts. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs on the system with heterogeneous multiprocessors.

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Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip

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