TY - GEN
T1 - Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip
AU - Ando, Yuki
AU - Ishida, Yukihito
AU - Honda, Shinya
AU - Takada, Hiroaki
AU - Edahiro, Masato
PY - 2015/2/26
Y1 - 2015/2/26
N2 - This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric by the high-bandwidth interconnect. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can realize various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by operating systems running on different types of processors. The problem is the cost to design and implement such communications. In order to overcome the problem and increase the design efficiency, we propose an automatic synthesis of inter-heterogeneous-processor communications from a general model description. The inter-heterogeneous-processor communications are realized using a shared memory and inter-processor interrupts. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs on the system with heterogeneous multiprocessors.
AB - This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric by the high-bandwidth interconnect. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can realize various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by operating systems running on different types of processors. The problem is the cost to design and implement such communications. In order to overcome the problem and increase the design efficiency, we propose an automatic synthesis of inter-heterogeneous-processor communications from a general model description. The inter-heterogeneous-processor communications are realized using a shared memory and inter-processor interrupts. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs on the system with heterogeneous multiprocessors.
UR - http://www.scopus.com/inward/record.url?scp=84925645534&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84925645534&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SATA.2015.7050464
DO - 10.1109/VLSI-SATA.2015.7050464
M3 - Conference contribution
AN - SCOPUS:84925645534
T3 - 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015
BT - 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015
Y2 - 8 January 2015 through 10 January 2015
ER -