AUTOMATIC TEST GENERATION SYSTEM FOR LARGE SCALE GATE ARRAYS.

T. Aikyo*, Y. Hatano, J. Ishii, N. Karasawa, S. Fujii

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the increase in the density and gate count of LSI and VLSI, test pattern generation becomes more and more difficult. One solution to this problem is scan path design. This paper describes an automatic test generation system for scan path design that has been applied to CMOS 20K gate arrays at Fujitsu. A feature of this system is automatic test generation for logic circuits with on-chip RAM, bidirectional buses, and clock control circuits using a time expanded modeling method and an extended PODEM algorithm with 17 signal values.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society International Conference
EditorsAlan G. Bell
PublisherIEEE
Pages445-449
Number of pages5
ISBN (Print)0818606924
Publication statusPublished - 1986
Externally publishedYes

Publication series

NameProceedings - IEEE Computer Society International Conference

ASJC Scopus subject areas

  • Engineering(all)

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