BAST: BIST-aided scan test. A new method for test cost reduction

Takashi Aikyo; Takahisa Hiraide; Michiaki Emori

doi:10.1002/ecjb.20356

BAST: BIST-aided scan test. A new method for test cost reduction

Takashi Aikyo^*, Takahisa Hiraide, Michiaki Emori

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increases in test cost arise with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method.

Original language	English
Pages (from-to)	58-65
Number of pages	8
Journal	Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume	90
Issue number	5
DOIs	https://doi.org/10.1002/ecjb.20356
Publication status	Published - 2007 May
Externally published	Yes

Keywords

ATPG
BIST
Fault coverage
Test compression
Test cost reduction

ASJC Scopus subject areas

Physics and Astronomy(all)
Computer Networks and Communications
Electrical and Electronic Engineering

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10.1002/ecjb.20356

Cite this

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abstract = "It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increases in test cost arise with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method.",

keywords = "ATPG, BIST, Fault coverage, Test compression, Test cost reduction",

author = "Takashi Aikyo and Takahisa Hiraide and Michiaki Emori",

year = "2007",

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N2 - It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increases in test cost arise with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method.

AB - It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increases in test cost arise with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method.

KW - ATPG

KW - BIST

KW - Fault coverage

KW - Test compression

KW - Test cost reduction

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BAST: BIST-aided scan test. A new method for test cost reduction

Abstract

Keywords

ASJC Scopus subject areas

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