BAST: BIST-aided scan test. A new method for test cost reduction

Takashi Aikyo*, Takahisa Hiraide, Michiaki Emori

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increases in test cost arise with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method.

Original languageEnglish
Pages (from-to)58-65
Number of pages8
JournalElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Issue number5
Publication statusPublished - 2007 May
Externally publishedYes


  • ATPG
  • BIST
  • Fault coverage
  • Test compression
  • Test cost reduction

ASJC Scopus subject areas

  • Physics and Astronomy(all)
  • Computer Networks and Communications
  • Electrical and Electronic Engineering


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