Bit-length optimization method for high-level synthesis based on non-linear programming technique

Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.

Original languageEnglish
Pages (from-to)3427-3434
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE89-A
Issue number12
DOIs
Publication statusPublished - 2006 Dec

Keywords

  • Bit-length optimization
  • HDL
  • High-level synthesis
  • Non-linear programming

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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