Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis

Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura, Katsumasa Watanabe

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In the hardware synthesis from a high-level language such as C, the bit length of variables is one of the key issues for the area and speed optimization. Usually, designers are required to optimize the bit-length of each variable manually using the time-consuming simulation on huge-data. In this paper, we propose an optimization method of the fractional bit length in the conversion from floating-point variables to fixed-point variables. The method is based on error propagation and the backward propagation of the accuracy limitation. The method is fully analytical and fast compared to simulation based methods.

Original languageEnglish
Pages (from-to)3184-3191
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE86-A
Issue number12
Publication statusPublished - 2003 Dec

Fingerprint

High-level Synthesis
Fractional Parts
Fixed point
Optimization
High level languages
Error Propagation
Floating point
Hardware
Optimization Methods
Simulation
Fractional
Optimise
Synthesis
Propagation
High level synthesis

Keywords

  • Bit length
  • HDL
  • High-level synthesis
  • Parallelizing compiler

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis. / Doi, Nobuhiro; Horiyama, Takashi; Nakanishi, Masaki; Kimura, Shinji; Watanabe, Katsumasa.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A, No. 12, 12.2003, p. 3184-3191.

Research output: Contribution to journalArticle

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