Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    Non-volatile memories are paid attention to as a promising alternative to memory design. Data stored in them still may be destructed due to crosstalk and radiation. We can restore the data by using error-correcting codes which require extra bits to correct bit errors. Further, non-volatile memories consume ten to hundred times more energy than normal memories in bit-writing. When we configure them using error-correcting codes, it is quite necessary to reduce writing bits. In this paper, we propose a method to generate a bit-write-reducing code with error-correcting ability. We first pick up an error-correcting code which can correct t-bit errors. We cluster its codeswords and generate a cluster graph satisfying the S-bit flip conditions. We assign a data to be written to each cluster. In other words, we generate one-to-many mapping from each data to the codewords in the cluster. We prove that, if the cluster graph is a complete graph, every data in a memory cell can be re-written into another data by flipping at most S bits keeping error-correcting ability to t bits. We further propose an efficient method to cluster error-correcting codewords. Experimental results demonstrate that, when we apply our bit-write-reducing code to MediaBench applications, it can reduce writing-bit counts by up to 28.2% and also energy consumption of non-volatile memory cells by up to 27.9% compared to existing error-correcting codes keeping the same error-correcting ability. This paper proposes the world-first theoretically near-optimal bit-write-reducing code with error-correcting ability based on the efficient coding theories.

    Original languageEnglish
    Title of host publication2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages682-689
    Number of pages8
    ISBN (Print)9781467383882
    DOIs
    Publication statusPublished - 2016 Jan 5
    Event34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 - Austin, United States
    Duration: 2015 Nov 22015 Nov 6

    Other

    Other34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
    CountryUnited States
    CityAustin
    Period15/11/215/11/6

    Fingerprint

    Data storage equipment
    Code generation
    Crosstalk
    Energy utilization
    Radiation

    ASJC Scopus subject areas

    • Computer Graphics and Computer-Aided Design

    Cite this

    Kojo, T., Tawada, M., Yanagisawa, M., & Togawa, N. (2016). Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories. In 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 (pp. 682-689). [7372636] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCAD.2015.7372636

    Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories. / Kojo, Tatsuro; Tawada, Masashi; Yanagisawa, Masao; Togawa, Nozomu.

    2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., 2016. p. 682-689 7372636.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Kojo, T, Tawada, M, Yanagisawa, M & Togawa, N 2016, Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories. in 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015., 7372636, Institute of Electrical and Electronics Engineers Inc., pp. 682-689, 34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, United States, 15/11/2. https://doi.org/10.1109/ICCAD.2015.7372636
    Kojo T, Tawada M, Yanagisawa M, Togawa N. Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories. In 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc. 2016. p. 682-689. 7372636 https://doi.org/10.1109/ICCAD.2015.7372636
    Kojo, Tatsuro ; Tawada, Masashi ; Yanagisawa, Masao ; Togawa, Nozomu. / Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories. 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 682-689
    @inproceedings{41e54bf791c74551b39f42c687955935,
    title = "Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories",
    abstract = "Non-volatile memories are paid attention to as a promising alternative to memory design. Data stored in them still may be destructed due to crosstalk and radiation. We can restore the data by using error-correcting codes which require extra bits to correct bit errors. Further, non-volatile memories consume ten to hundred times more energy than normal memories in bit-writing. When we configure them using error-correcting codes, it is quite necessary to reduce writing bits. In this paper, we propose a method to generate a bit-write-reducing code with error-correcting ability. We first pick up an error-correcting code which can correct t-bit errors. We cluster its codeswords and generate a cluster graph satisfying the S-bit flip conditions. We assign a data to be written to each cluster. In other words, we generate one-to-many mapping from each data to the codewords in the cluster. We prove that, if the cluster graph is a complete graph, every data in a memory cell can be re-written into another data by flipping at most S bits keeping error-correcting ability to t bits. We further propose an efficient method to cluster error-correcting codewords. Experimental results demonstrate that, when we apply our bit-write-reducing code to MediaBench applications, it can reduce writing-bit counts by up to 28.2{\%} and also energy consumption of non-volatile memory cells by up to 27.9{\%} compared to existing error-correcting codes keeping the same error-correcting ability. This paper proposes the world-first theoretically near-optimal bit-write-reducing code with error-correcting ability based on the efficient coding theories.",
    author = "Tatsuro Kojo and Masashi Tawada and Masao Yanagisawa and Nozomu Togawa",
    year = "2016",
    month = "1",
    day = "5",
    doi = "10.1109/ICCAD.2015.7372636",
    language = "English",
    isbn = "9781467383882",
    pages = "682--689",
    booktitle = "2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",

    }

    TY - GEN

    T1 - Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

    AU - Kojo, Tatsuro

    AU - Tawada, Masashi

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2016/1/5

    Y1 - 2016/1/5

    N2 - Non-volatile memories are paid attention to as a promising alternative to memory design. Data stored in them still may be destructed due to crosstalk and radiation. We can restore the data by using error-correcting codes which require extra bits to correct bit errors. Further, non-volatile memories consume ten to hundred times more energy than normal memories in bit-writing. When we configure them using error-correcting codes, it is quite necessary to reduce writing bits. In this paper, we propose a method to generate a bit-write-reducing code with error-correcting ability. We first pick up an error-correcting code which can correct t-bit errors. We cluster its codeswords and generate a cluster graph satisfying the S-bit flip conditions. We assign a data to be written to each cluster. In other words, we generate one-to-many mapping from each data to the codewords in the cluster. We prove that, if the cluster graph is a complete graph, every data in a memory cell can be re-written into another data by flipping at most S bits keeping error-correcting ability to t bits. We further propose an efficient method to cluster error-correcting codewords. Experimental results demonstrate that, when we apply our bit-write-reducing code to MediaBench applications, it can reduce writing-bit counts by up to 28.2% and also energy consumption of non-volatile memory cells by up to 27.9% compared to existing error-correcting codes keeping the same error-correcting ability. This paper proposes the world-first theoretically near-optimal bit-write-reducing code with error-correcting ability based on the efficient coding theories.

    AB - Non-volatile memories are paid attention to as a promising alternative to memory design. Data stored in them still may be destructed due to crosstalk and radiation. We can restore the data by using error-correcting codes which require extra bits to correct bit errors. Further, non-volatile memories consume ten to hundred times more energy than normal memories in bit-writing. When we configure them using error-correcting codes, it is quite necessary to reduce writing bits. In this paper, we propose a method to generate a bit-write-reducing code with error-correcting ability. We first pick up an error-correcting code which can correct t-bit errors. We cluster its codeswords and generate a cluster graph satisfying the S-bit flip conditions. We assign a data to be written to each cluster. In other words, we generate one-to-many mapping from each data to the codewords in the cluster. We prove that, if the cluster graph is a complete graph, every data in a memory cell can be re-written into another data by flipping at most S bits keeping error-correcting ability to t bits. We further propose an efficient method to cluster error-correcting codewords. Experimental results demonstrate that, when we apply our bit-write-reducing code to MediaBench applications, it can reduce writing-bit counts by up to 28.2% and also energy consumption of non-volatile memory cells by up to 27.9% compared to existing error-correcting codes keeping the same error-correcting ability. This paper proposes the world-first theoretically near-optimal bit-write-reducing code with error-correcting ability based on the efficient coding theories.

    UR - http://www.scopus.com/inward/record.url?scp=84964450422&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84964450422&partnerID=8YFLogxK

    U2 - 10.1109/ICCAD.2015.7372636

    DO - 10.1109/ICCAD.2015.7372636

    M3 - Conference contribution

    SN - 9781467383882

    SP - 682

    EP - 689

    BT - 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015

    PB - Institute of Electrical and Electronics Engineers Inc.

    ER -