Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder

Chen Xianmin, Liu Peilin, Zhu Jiayi, Zhou Dajiang, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

In this paper, we present a cache scheme targeting hardware implementation to reduce the bandwidth of motion compensation, and a block-pipelining strategy to hide long latency of the external memory in high definition H.264/AVC video decoder. Hardware architecture is also implemented for the proposed algorithms. Experimental results show that the cache succeeds in reducing external memory bandwidth of motion compensation by 66%-78% and the block-pipelining strategy can solve the latency problem better than previous solutions. Our proposed hardware architecture can averagely process one macroblock within 297 cycles, capable of real-time processing 1920x1088@30fps H.264 sequence at lower than 80MHz.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages1069-1072
Number of pages4
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei
Duration: 2009 May 242009 May 27

Other

Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CityTaipei
Period09/5/2409/5/27

Fingerprint

Motion compensation
Hardware
Bandwidth
Data storage equipment
Computer hardware
Processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Xianmin, C., Peilin, L., Jiayi, Z., Dajiang, Z., & Goto, S. (2009). Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1069-1072). [5117944] https://doi.org/10.1109/ISCAS.2009.5117944

Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder. / Xianmin, Chen; Peilin, Liu; Jiayi, Zhu; Dajiang, Zhou; Goto, Satoshi.

Proceedings - IEEE International Symposium on Circuits and Systems. 2009. p. 1069-1072 5117944.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Xianmin, C, Peilin, L, Jiayi, Z, Dajiang, Z & Goto, S 2009, Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder. in Proceedings - IEEE International Symposium on Circuits and Systems., 5117944, pp. 1069-1072, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, 09/5/24. https://doi.org/10.1109/ISCAS.2009.5117944
Xianmin C, Peilin L, Jiayi Z, Dajiang Z, Goto S. Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder. In Proceedings - IEEE International Symposium on Circuits and Systems. 2009. p. 1069-1072. 5117944 https://doi.org/10.1109/ISCAS.2009.5117944
Xianmin, Chen ; Peilin, Liu ; Jiayi, Zhu ; Dajiang, Zhou ; Goto, Satoshi. / Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder. Proceedings - IEEE International Symposium on Circuits and Systems. 2009. pp. 1069-1072
@inproceedings{87984b35c686427ebce485f6b3aaac76,
title = "Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder",
abstract = "In this paper, we present a cache scheme targeting hardware implementation to reduce the bandwidth of motion compensation, and a block-pipelining strategy to hide long latency of the external memory in high definition H.264/AVC video decoder. Hardware architecture is also implemented for the proposed algorithms. Experimental results show that the cache succeeds in reducing external memory bandwidth of motion compensation by 66{\%}-78{\%} and the block-pipelining strategy can solve the latency problem better than previous solutions. Our proposed hardware architecture can averagely process one macroblock within 297 cycles, capable of real-time processing 1920x1088@30fps H.264 sequence at lower than 80MHz.",
author = "Chen Xianmin and Liu Peilin and Zhu Jiayi and Zhou Dajiang and Satoshi Goto",
year = "2009",
doi = "10.1109/ISCAS.2009.5117944",
language = "English",
isbn = "9781424438280",
pages = "1069--1072",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

}

TY - GEN

T1 - Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder

AU - Xianmin, Chen

AU - Peilin, Liu

AU - Jiayi, Zhu

AU - Dajiang, Zhou

AU - Goto, Satoshi

PY - 2009

Y1 - 2009

N2 - In this paper, we present a cache scheme targeting hardware implementation to reduce the bandwidth of motion compensation, and a block-pipelining strategy to hide long latency of the external memory in high definition H.264/AVC video decoder. Hardware architecture is also implemented for the proposed algorithms. Experimental results show that the cache succeeds in reducing external memory bandwidth of motion compensation by 66%-78% and the block-pipelining strategy can solve the latency problem better than previous solutions. Our proposed hardware architecture can averagely process one macroblock within 297 cycles, capable of real-time processing 1920x1088@30fps H.264 sequence at lower than 80MHz.

AB - In this paper, we present a cache scheme targeting hardware implementation to reduce the bandwidth of motion compensation, and a block-pipelining strategy to hide long latency of the external memory in high definition H.264/AVC video decoder. Hardware architecture is also implemented for the proposed algorithms. Experimental results show that the cache succeeds in reducing external memory bandwidth of motion compensation by 66%-78% and the block-pipelining strategy can solve the latency problem better than previous solutions. Our proposed hardware architecture can averagely process one macroblock within 297 cycles, capable of real-time processing 1920x1088@30fps H.264 sequence at lower than 80MHz.

UR - http://www.scopus.com/inward/record.url?scp=70350142436&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70350142436&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2009.5117944

DO - 10.1109/ISCAS.2009.5117944

M3 - Conference contribution

AN - SCOPUS:70350142436

SN - 9781424438280

SP - 1069

EP - 1072

BT - Proceedings - IEEE International Symposium on Circuits and Systems

ER -