Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder

Chen Xianmin, Liu Peilin, Zhu Jiayi, Zhou Dajiang, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

In this paper, we present a cache scheme targeting hardware implementation to reduce the bandwidth of motion compensation, and a block-pipelining strategy to hide long latency of the external memory in high definition H.264/AVC video decoder. Hardware architecture is also implemented for the proposed algorithms. Experimental results show that the cache succeeds in reducing external memory bandwidth of motion compensation by 66%-78% and the block-pipelining strategy can solve the latency problem better than previous solutions. Our proposed hardware architecture can averagely process one macroblock within 297 cycles, capable of real-time processing 1920x1088@30fps H.264 sequence at lower than 80MHz.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages1069-1072
Number of pages4
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei
Duration: 2009 May 242009 May 27

Other

Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CityTaipei
Period09/5/2409/5/27

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Xianmin, C., Peilin, L., Jiayi, Z., Dajiang, Z., & Goto, S. (2009). Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1069-1072). [5117944] https://doi.org/10.1109/ISCAS.2009.5117944