Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS

Xiao Xu, Xin Yang, Taufiq Alif Kurniawan, Toshihiko Yoshimasu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5-dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.

Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages653-655
Number of pages3
ISBN (Print)9781479983636
DOIs
Publication statusPublished - 2015 Sep 30
Event11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore
Duration: 2015 Jun 12015 Jun 4

Other

Other11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
CountrySingapore
CitySingapore
Period15/6/115/6/4

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Keywords

  • floating body technique
  • high isolation
  • SPDT switch IC
  • stacked transistor
  • wideband

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Xu, X., Yang, X., Kurniawan, T. A., & Yoshimasu, T. (2015). Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 653-655). [7285200] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285200