Buffer planning for 3D ICs

Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    With recent advance of VLSI design, interconnect delay plays dominant role in the chip performance. 3D integration, which stacks multiple device layers, greatly reduces interconnect delay. Buffer insertion, as another approach to reduce wire delay, is still necessary to further optimize interconnects. In this paper, a buffer planning algorithm at floorplanning stage for 3D ICs is proposed. Firstly, we reduce buffer insertion to a dynamic programming path problem. Then we show its potential to handle the 3D buffer insertion problem. At the same time, vertical interlayer vias are also planned. At last, buffer planning is integrated with floorplanning to optimize the packing so that not only area and wire length reach a satisfying value, timing performance is also optimized.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    Pages1735-1738
    Number of pages4
    DOIs
    Publication statusPublished - 2009
    Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei
    Duration: 2009 May 242009 May 27

    Other

    Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
    CityTaipei
    Period09/5/2409/5/27

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Dong, S., Bai, H., Hong, X., & Goto, S. (2009). Buffer planning for 3D ICs. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1735-1738). [5118110] https://doi.org/10.1109/ISCAS.2009.5118110