Buffer planning for IP placement using sliced-LFF

Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto

Research output: Contribution to journalArticle

Abstract

IP cores are widely used in modern SOC designs. Hierarchical design has been employed for the growing design complexity, which stimulates the need for fixed-outline floorplanning. Meanwhile, buffer insertion is usually adopted to meet the timing requirement. In this paper, buffer insertion is considered with a fixed-outline constraint using Less Flexibility First (LFF) algorithm. Compared with Simulated Annealing (SA), our work is able to distinguish geometric differences between two floorplan candidates, even if they have the same topological structure. This is helpful to get a better result for buffer planning since buffer insertion is quite sensitive to a geometric change. We also extend the previous LFF to a more robust version called Sliced-LFF to improve buffer planning. Moreover, a 2-staged LFF framework and a post-greedy procedure are introduced based on our net-classing strategy and finally achieve a significant improvement on the success rate of buffer insertion (40.7 and 37.1 in different feature sizes). Moreover, our work is much faster than SA, since it is deterministic without iterations.

Original languageEnglish
Article number530851
JournalVLSI Design
Volume2011
DOIs
Publication statusPublished - 2011

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Graphics and Computer-Aided Design

Cite this

He, O., Dong, S., Bian, J., & Goto, S. (2011). Buffer planning for IP placement using sliced-LFF. VLSI Design, 2011, [530851]. https://doi.org/10.1155/2011/530851