Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Y. Hirano, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, Masahide Inuishi, T. Nishimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

To allow the application of floating silicon on insulator (SOI) technology on analog circuits, the full body-fixing structure can be used. However, this technique may cause some shortcomings in scalability and layout compatibility. The partial trench isolation (PTI) technique is proposed, in which the body potential is fixed through the region under the trench oxide. With the PTI technology, the floating-body effects are eliminated while maintaining SOI-inherent merits and scalable deep sub-quarter micron LSIs can be realized using accumulated bulk design properties without layout modification.

Original languageEnglish
Title of host publicationIEEE International SOI Conference
PublisherIEEE
Pages131-132
Number of pages2
Publication statusPublished - 1999
Externally publishedYes
EventThe 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference - Rohnert Park, CA, USA
Duration: 1999 Oct 41999 Oct 7

Other

OtherThe 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference
CityRohnert Park, CA, USA
Period99/10/499/10/7

Fingerprint

Silicon on insulator technology
Analog circuits
Scalability
Silicon
Oxides

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Hirano, Y., Maeda, S., Matsumoto, T., Nii, K., Iwamatsu, T., Yamaguchi, Y., ... Nishimura, T. (1999). Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI). In IEEE International SOI Conference (pp. 131-132). IEEE.

Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI). / Hirano, Y.; Maeda, S.; Matsumoto, T.; Nii, K.; Iwamatsu, T.; Yamaguchi, Y.; Ipposhi, T.; Kawashima, H.; Maegawa, S.; Inuishi, Masahide; Nishimura, T.

IEEE International SOI Conference. IEEE, 1999. p. 131-132.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hirano, Y, Maeda, S, Matsumoto, T, Nii, K, Iwamatsu, T, Yamaguchi, Y, Ipposhi, T, Kawashima, H, Maegawa, S, Inuishi, M & Nishimura, T 1999, Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI). in IEEE International SOI Conference. IEEE, pp. 131-132, The 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference, Rohnert Park, CA, USA, 99/10/4.
Hirano Y, Maeda S, Matsumoto T, Nii K, Iwamatsu T, Yamaguchi Y et al. Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI). In IEEE International SOI Conference. IEEE. 1999. p. 131-132
Hirano, Y. ; Maeda, S. ; Matsumoto, T. ; Nii, K. ; Iwamatsu, T. ; Yamaguchi, Y. ; Ipposhi, T. ; Kawashima, H. ; Maegawa, S. ; Inuishi, Masahide ; Nishimura, T. / Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI). IEEE International SOI Conference. IEEE, 1999. pp. 131-132
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