Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Y. Hirano; S. Maeda; T. Matsumoto; K. Nii; T. Iwamatsu; Y. Yamaguchi; T. Ipposhi; H. Kawashima; S. Maegawa; M. Inuishi; T. Nishimura

Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Y. Hirano^*, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, M. Inuishi, T. Nishimura

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

5 Citations (Scopus)

Abstract

To allow the application of floating silicon on insulator (SOI) technology on analog circuits, the full body-fixing structure can be used. However, this technique may cause some shortcomings in scalability and layout compatibility. The partial trench isolation (PTI) technique is proposed, in which the body potential is fixed through the region under the trench oxide. With the PTI technology, the floating-body effects are eliminated while maintaining SOI-inherent merits and scalable deep sub-quarter micron LSIs can be realized using accumulated bulk design properties without layout modification.

Original language	English
Pages	131-132
Number of pages	2
Publication status	Published - 1999 Dec 1
Externally published	Yes
Event	The 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference - Rohnert Park, CA, USA Duration: 1999 Oct 4 → 1999 Oct 7

Other

Other	The 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference
City	Rohnert Park, CA, USA
Period	99/10/4 → 99/10/7

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Hirano, Y., Maeda, S., Matsumoto, T., Nii, K., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Kawashima, H., Maegawa, S., Inuishi, M., & Nishimura, T. (1999). Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI). 131-132. Paper presented at The 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference, Rohnert Park, CA, USA.

Hirano, Y, Maeda, S, Matsumoto, T, Nii, K, Iwamatsu, T, Yamaguchi, Y, Ipposhi, T, Kawashima, H, Maegawa, S, Inuishi, M & Nishimura, T 1999, 'Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)', Paper presented at The 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference, Rohnert Park, CA, USA, 99/10/4 - 99/10/7 pp. 131-132.

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AU - Hirano, Y.

AU - Maeda, S.

AU - Matsumoto, T.

AU - Nii, K.

AU - Iwamatsu, T.

AU - Yamaguchi, Y.

AU - Ipposhi, T.

AU - Kawashima, H.

AU - Maegawa, S.

AU - Inuishi, M.

AU - Nishimura, T.

PY - 1999/12/1

Y1 - 1999/12/1

N2 - To allow the application of floating silicon on insulator (SOI) technology on analog circuits, the full body-fixing structure can be used. However, this technique may cause some shortcomings in scalability and layout compatibility. The partial trench isolation (PTI) technique is proposed, in which the body potential is fixed through the region under the trench oxide. With the PTI technology, the floating-body effects are eliminated while maintaining SOI-inherent merits and scalable deep sub-quarter micron LSIs can be realized using accumulated bulk design properties without layout modification.

AB - To allow the application of floating silicon on insulator (SOI) technology on analog circuits, the full body-fixing structure can be used. However, this technique may cause some shortcomings in scalability and layout compatibility. The partial trench isolation (PTI) technique is proposed, in which the body potential is fixed through the region under the trench oxide. With the PTI technology, the floating-body effects are eliminated while maintaining SOI-inherent merits and scalable deep sub-quarter micron LSIs can be realized using accumulated bulk design properties without layout modification.

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T2 - The 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference

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ER -

Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Abstract

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ASJC Scopus subject areas

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