Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Y. Hirano, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, M. Inuishi, T. Nishimura

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Abstract

To allow the application of floating silicon on insulator (SOI) technology on analog circuits, the full body-fixing structure can be used. However, this technique may cause some shortcomings in scalability and layout compatibility. The partial trench isolation (PTI) technique is proposed, in which the body potential is fixed through the region under the trench oxide. With the PTI technology, the floating-body effects are eliminated while maintaining SOI-inherent merits and scalable deep sub-quarter micron LSIs can be realized using accumulated bulk design properties without layout modification.

Original languageEnglish
Pages131-132
Number of pages2
Publication statusPublished - 1999 Dec 1
Externally publishedYes
EventThe 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference - Rohnert Park, CA, USA
Duration: 1999 Oct 41999 Oct 7

Other

OtherThe 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference
CityRohnert Park, CA, USA
Period99/10/499/10/7

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Hirano, Y., Maeda, S., Matsumoto, T., Nii, K., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Kawashima, H., Maegawa, S., Inuishi, M., & Nishimura, T. (1999). Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI). 131-132. Paper presented at The 25th Annual IEEE International Silicon-on-Insualtor (SOI) Conference, Rohnert Park, CA, USA, .