Abstract
Transistor performance improvement has been strongly required for work toward highly integrated intelligent system LSIs. To meet this demand, silicon on insulator (SOI) has become of major interest for next generation devices, because it can offer durable device scaling as compared with bulk devices (Schepis et al. 1997). The critical issues for SOI are floating-body effects such as deterioration in drain current (Matsumoto et al. 1999), dynamic threshold voltage instability (Lu et al. 1997), and increased soft error rate (Wada et al. 1998). These have restricted the application of floating SOI, especially to analog circuits. Some circuit modifications and body contact insertions are necessary. A full body-fixing structure is another approach and some techniques have been proposed (Koh et al. 1997; Iwamatsu et al. 1995). However, when using these techniques, there have been some shortcomings in terms of scalability and layout compatibility. In this report, we propose a partial trench isolation (PTI) technique in which the body potential is fixed through the region under the trench oxide. With the PTI technology, we can eliminate floating-body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification. Moreover, the feasibility for ULSIs is demonstrated by a fully functional 4 Mbit SRAM.
| Original language | English |
|---|---|
| Title of host publication | 1999 IEEE International SOI Conference, SOI 1999 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 131-132 |
| Number of pages | 2 |
| ISBN (Print) | 0780354567, 9780780354562 |
| DOIs | |
| Publication status | Published - 1999 Jan 1 |
| Externally published | Yes |
| Event | 25th Annual IEEE International Silicon-on-Insulator Conference, SOI 19999 - Rohnert Park, United States Duration: 1999 Oct 4 → 1999 Oct 7 |
Other
| Other | 25th Annual IEEE International Silicon-on-Insulator Conference, SOI 19999 |
|---|---|
| Country | United States |
| City | Rohnert Park |
| Period | 99/10/4 → 99/10/7 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI). / Hirano, Y.; Maeda, S.; Matsumoto, T.; Nii, K.; Iwamatsu, T.; Yamaguchi, Y.; Ipposhi, T.; Kawashima, H.; Maegawa, S.; Inuishi, Masahide; Nishimura, T.
1999 IEEE International SOI Conference, SOI 1999 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 1999. p. 131-132 819887.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)
AU - Hirano, Y.
AU - Maeda, S.
AU - Matsumoto, T.
AU - Nii, K.
AU - Iwamatsu, T.
AU - Yamaguchi, Y.
AU - Ipposhi, T.
AU - Kawashima, H.
AU - Maegawa, S.
AU - Inuishi, Masahide
AU - Nishimura, T.
PY - 1999/1/1
Y1 - 1999/1/1
N2 - Transistor performance improvement has been strongly required for work toward highly integrated intelligent system LSIs. To meet this demand, silicon on insulator (SOI) has become of major interest for next generation devices, because it can offer durable device scaling as compared with bulk devices (Schepis et al. 1997). The critical issues for SOI are floating-body effects such as deterioration in drain current (Matsumoto et al. 1999), dynamic threshold voltage instability (Lu et al. 1997), and increased soft error rate (Wada et al. 1998). These have restricted the application of floating SOI, especially to analog circuits. Some circuit modifications and body contact insertions are necessary. A full body-fixing structure is another approach and some techniques have been proposed (Koh et al. 1997; Iwamatsu et al. 1995). However, when using these techniques, there have been some shortcomings in terms of scalability and layout compatibility. In this report, we propose a partial trench isolation (PTI) technique in which the body potential is fixed through the region under the trench oxide. With the PTI technology, we can eliminate floating-body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification. Moreover, the feasibility for ULSIs is demonstrated by a fully functional 4 Mbit SRAM.
AB - Transistor performance improvement has been strongly required for work toward highly integrated intelligent system LSIs. To meet this demand, silicon on insulator (SOI) has become of major interest for next generation devices, because it can offer durable device scaling as compared with bulk devices (Schepis et al. 1997). The critical issues for SOI are floating-body effects such as deterioration in drain current (Matsumoto et al. 1999), dynamic threshold voltage instability (Lu et al. 1997), and increased soft error rate (Wada et al. 1998). These have restricted the application of floating SOI, especially to analog circuits. Some circuit modifications and body contact insertions are necessary. A full body-fixing structure is another approach and some techniques have been proposed (Koh et al. 1997; Iwamatsu et al. 1995). However, when using these techniques, there have been some shortcomings in terms of scalability and layout compatibility. In this report, we propose a partial trench isolation (PTI) technique in which the body potential is fixed through the region under the trench oxide. With the PTI technology, we can eliminate floating-body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification. Moreover, the feasibility for ULSIs is demonstrated by a fully functional 4 Mbit SRAM.
UR - http://www.scopus.com/inward/record.url?scp=85054393641&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85054393641&partnerID=8YFLogxK
U2 - 10.1109/SOI.1999.819887
DO - 10.1109/SOI.1999.819887
M3 - Conference contribution
SN - 0780354567
SN - 9780780354562
SP - 131
EP - 132
BT - 1999 IEEE International SOI Conference, SOI 1999 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -