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Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)
Y. Hirano, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, M. Inuishi, T. Nishimura
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution